The 14-bit LTC2262 analog-to-digital converter (ADC) from Linear Technology Corp. dissipates 149 mW, which is less than a third the power of competitive solutions, according to the company. Also, Linear says that this low-power, 150-Msample/s device enables portable applications limited by stringent power budgets to extend their performance capabilities, as well as provide higher operating efficiency and reduced recurring operating costs for 3G/4G Long-Term Evolution (LTE) and WiMAX basestation equipment.

Article Tools

• 

In addition, the LTC2262 integrates two unique features for reducing digital feedback in situations where even good layout practice may fail. In combination with low power, these features ease the task of designing with high-speed ADCs in a wide variety of applications, according to Linear, including portable medical imaging and ultrasound, portable test and instrumentation, non-destructive test equipment, software-defined radios, and cellular basestations.

Digital feedback occurs when energy from ADC outputs couples back into the analog section, causing interaction that appears as an odd shaping in the noise floor and spurs in the ADC output spectrum. The worst situation is at midscale, where all outputs are changing from ones to zeroes, or vice versa, generating large ground currents that couple back into the input. To combat this effect, the LTC2262’s proprietary alternate bit polarity (ABP) mode inverts all of the odd bits before the output buffers to equalize the number of ones and zeroes switching.

This method effectively cancels the large ground plane currents that contribute to digital feedback. In addition to the ABP mode, an optional data output randomizer decorrelates the digital output to reduce the likelihood of repetitive code patterns that couple back into the ADC input, causing unwanted tones in the output spectrum. Both digital feedback reduction techniques have proven to improve spurious-free dynamic range (SFDR) performance by 10 to 15 dB.

Operating from a 1.8-V analog supply, the LTC2262 achieves significant power savings without sacrificing ac performance, Linear says. It offers a signal-to-noise ratio (SNR) performance of 72.8 dB and SFDR or 88 dB at baseband. Its 0.17-ps rms jitter enables the undersampling of IF frequencies with excellent noise performance, according to the company.

The LTC2262’s digital outputs can be set to full-rate CMOS, double-data-rate (DDR) CMOS, or double-data-rate low-voltage differential signaling  (LVDS). DDR digital outputs allow data to be transmitted on both the rising edge and the falling edge of the clock, reducing the number of data lines needed by half. A separate output power supply permits the CMOS output swing to range form 1.2 to 1.8 V.

Offered in a 6- by 6-mm quad flat no-lead (QFN) package, the LTC2262 includes a clock duty cycle stabilizer circuit to facilitate non-50% clock duty cycles, programmable digital output timing, programmable LVDS output current, and optional LVDS output termination. These features combine to make the data transmission between the ADC and the digital receiver more flexible, Linear says.

The LTC2262 is available in commercial and industrial temperature ranges. The 14-bit LTC2262-14 costs $57.00 each and the 12-bit LTC2262-12 costs $35.00 each, both in 1000-unit quantities. Demonstration boards and samples are available online at the company’s Web site. All parts are available in optional lead-free packages for compliance with the European Union’s Restrictions on Hazardous Substances (RoHS).