Zarlink Semiconductor’s ZL30117 single-chip, ultra-low jitter synchronizer solves the timing challenges posed by the popular AdvancedTCA (telecommunications computing architecture), AMC (advanced mezzanine card) and MicroTCA architectures. The analog/digital PLL (phase-locked loop) achieves low jitter, with robust and stable clocks for SONET/SDH in open-platform telecom architectures.

Article Tools

• 

ATCA is gaining acceptance as an open architecture for adaptable, modular design in next-generation communications equipment. AMC is an open specification for mezzanine cards optimized for, but not limited to, ATCA applications. MicroTCA is a cost-optimized architecture that uses AMCs that are plugged directly into backplanes. By using standard hardware and software components from multiple vendors, ATCA, AMC, and MicroTCA reduce the time and cost-to-market of high-performance, high-density systems, but present challenges for achieving carrier-grade synchronization reliability.

The ZL30117 synchronizer offers robust features for AMCs used in ATCA and MicroTCA designs. While easy to use and adaptable, AMCs do not provide redundant timing reference inputs to support carrier-grade timing. The holdover capability of the ZL30117 chip enables it to ride out the complete loss of its incoming reference, which can occur when switching from a failed clock unit to a backup clock unit. The ZL30117 PLL continues to operate in full compliance with network requirements for several seconds after losing its reference, allowing time for the system to provide another reference source to the AMC.

The device accepts three reference inputs, supporting clock frequencies in any multiple of 8 kHz up to 77.76 MHz, as well as supporting 2 kHz. The ZL30117 can directly lock to any of the standard clock input frequencies available to an AMC in an ATCA or MicroTCA application.

The ZL30117 device is the newest in Zarlink’s family of synchronization chips. It consumes less than 0.9 W and measures 9 mm x 9 mm.