Analog Devices has released a line of 18 analog-to-digital converters (ADCs) with resolutions ranging from 10 to 16 bits for power-sensitive communications, industrial, portable, and instrumentation equipment. According to the company, they reduce power consumption by as much as 60% compared to many competing ADCs while maintaining best-in-class noise performance and dynamic range.

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The line’s integration and energy savings allow system engineers to increase channel counts without increasing a product’s board area or power consumption, enabling higher call volume in cellular basestations or improved image resolution in portable devices. The ADCs also enable improved system performance while extending battery life in handheld devices.

For example, the 125-Msample/s, 16-bit, dual-channel AD9268 achieves a 78-dB signal-to-noise ratio (SNR) and 90-dB spurious-free dynamic range (SFDR) to a 70-MHz analog input frequency while consuming 376 mW per channel. It is available in a 9- by 9-mm lead-free chip-scale package (LFCSP) that’s pin-compatible with ADI’s other low-power ADCs for faster upgrades, debug, and time-to-market. It’s available in 80- and 105-Msample/s options as well.

The dual-channel, 14-bit AD9521 is available in the same 64-lead LFCSP pin-compatible footprint with 20-, 40-, 65-, and 80-Msample/s speed grades. With 73.5-dB SNR and 85-dB SFDR to a 70-MHz analog input frequency, it dissipates 86 mW per channel at 80 Msamples/s, improving power efficiency by more than 50% over competing 14-bit ADCs, according to ADI.

All of the ADCs in the line operate from a single 1.8-V analog power supply and feature a high-performance sample-and-hold circuit and on-chip voltage reference. The AD9251 models offer a separate driver supply to accommodate 1.8- or 3.3-V CMOS logic outputs, while the AD9268 devices offer 1.8-V low-voltage differential signaling or CMOS outputs. 

The ADC cores use a multistage, differential pipelined architecture with integrated output error-correction logic. The ADCs also include features designed to maximize flexibility and minimize system cost, including programmable clock and data alignment and programmable digital test-pattern generation. The available patterns include built-in, deterministic, and pseudo-random patterns, as well as definable test patterns users can enter via the serial port interface (SPI).

Sampling now, production quantities of the ADCs will be available in June 2009.