Residing in thin-shrink small-outline packages (TSSOPs) and quad flat no-lead (QFN) packages, the CDCLVC11xx, CDCLVD12xx/21xx, and CDCLVP12xx/21xx clock buffer families from Texas Instruments achieve the industry’s lowest additive jitter, according to the company. Depending on the family, the devices support frequencies up to 2 GHz (LVPECL), 800 MHz (LVDS), and 250 MHz (LVCMOS).

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Delivering LVCMOS outputs, the devices in the CDCLVC11xx family generate two, three, four, six, eight, 10, or 12 clock outputs and specify a jitter of less than 100 fsRMS (12 kHz to 20 MHz). The CDCLVD12xx/21xx devices generate four, eight, 12, or 16 LVDS outputs from one of two selectable LVCMOS, LVDS, or LVPECL inputs with a jitter of less than 300 fsRMS (10 kHz to 20 MHz). Providing LVPECL outputs, the CDCLVP12xx/21xx buffers generate four, eight, 12, or 16 outputs from one of two selectable LVCMOS, LVDS, or LVPECL inputs and exhibit jitter less than 100 fsRMS (10 kHz to 20 MHz).

A four-output version from the CDCLVC11xx, CDCLVD12xx/21xx, and CDCLVP12xx/21xx families costs $0.90, $2.85, and $3.30 each/1000, respectively.

Texas Instruments