According to market research firm In-Stat, worldwide sales of mobile phones will rise from 935 million units in 2006 to more than double that in 2011 (“The Big Trends For Cell Phones, 2006-2011,” May 2006). With cell-phone manufacturers now producing more than 1 billion units annually, this has become one of the most competitive markets to be addressed by the semiconductor industry.

Because cost is king, manufacturers are under increasing pressure to produce chipsets that are smaller and more cost-effective while offering broader feature sets. The big problem is determining how you integrate a power amplifier (PA) on the same chip with all the other cell-phone circuitry.

The CMOS PA Challenge

Some experts say that specialty processes such as gallium arsenide (GaAs), laterally diffused MOS (LDMOS), or silicon-germanium (SiGe) bipolar CMOS (biCMOS) with less precise geometries may offer the short-term cost advantage and linear modulation demanded by manufacturers and designers.

However, the economies of scale inherent in silicon CMOS have driven the semiconductor industry to make significant investments in this process technology, creating capabilities and capacity that have outlasted and will continue to outlast any niche process offerings.

For example, transceiver blocks previously required specialty biCMOS processes from vendors such as Infineon, NXP, and Skyworks. But they have long since been implemented in CMOS and, in some cases, integrated with the handset’s main processor inside a system-on-a-chip (SoC). Designers have repeatedly found that implementing an analog block in standard CMOS has paid off in the long run, despite the hurdles of implementing challenging circuit blocks in a less forgiving process.

Despite these advances, though, the CMOS process has not been able to successfully penetrate the PA block, which continues to remain a key element within the cell phone. It is still considered the most difficult block to implement both as a component and as part of the final application.

Up until now, the PA block has been developed using a specialty GaAs or LDMOS process coupled with a hybrid module packaging technology—in total an expensive manufacturing flow, which has made it a substantial part of the cell-phone bill of materials. The specialty semiconductor process is required to provide a high-gain, high-frequency transistor element with a high breakdown voltage. The hybrid packaging technology provides high-Q passive components to generate the 50-Ω matching circuit.

Implementing in standard CMOS means the designer has to live without enhanced transistors and high-Q passives. This makes the development of a fully integrated PA extremely challenging. A smaller challenge is simply transferring the active core from a specialty process to CMOS, but the cost savings simply aren’t sufficient.

In current GaAs implementations, a high percentage of the cost is incurred in the manufacturing of the multichip module, with its expensive substrates and requirement for the sourcing and assembly of surface-mount (SMT) components. Integrating the 50-Ω match on die, therefore, was necessary to eliminate the need for the module.

Analysis of the Problem

A first step in taking on the challenge of implementing a high-power non-module PA in CMOS, specifically a quad-band GSM/GPRS device, is to examine the conventional techniques employed to realize existing PAs.

In the cell-phone environment, operation must be achieved from a battery that produces a relatively low voltage. Nominally, nickel-metal-hydride (NiMH) or lithium-ion (Li-ion) cells produce a nominal voltage of around 3.6 V. Printed-circuit board (PCB) trace resistance, coupled with the order of magnitude of current drawn, means that the available voltage at the PA is around 3.5 V. Without the use of a load impedance transformation, the maximum power that can be generated into a 50-Ω load is provided by the equation:

Given that the GSM standard requires output power levels of around +35 dBm or greater than 3 W, some kind of impedance transformation is required. The normal implementation of an impedance transformation places a resonant match at the output of the main power stage (Fig. 1).

Resonant matching structures require high-Q elements to maintain a reasonable passive efficiency, making it difficult to implement them on a typical CMOS process where Qs in the range of only 5 to 15 are achievable.

Another approach is to use a transformer type match. A transformer has the benefit that inductively stored energy is low compared to a resonant match, meaning that a transformer structure can have lower Q and still perform the impedance transformation to the same degree of satisfaction (Fig. 2). Simply using a conventional transformer structure does not solve the problem, as the primary and secondary windings require inductance values that aren’t easy to implement.