The SOI Industry Consortium announced results of an assessment and characterization of fully-depleted Silicon-on-Insulator (FD-SOI) technology, demonstrating that this advanced complimentary metal-oxide semiconductor (CMOS) silicon technology is well suited to address the increasing low-power, high-performance requirements for mobile and consumer applications. A joint collaboration between Consortium members—ARM, GlobalFoundries, IBM, STMicroelectronics, Soitec, and CEA-Leti—has demonstrated benefits of planar FD-SOI technology for these applications based on an ARM processor.

Article Tools

• 

The SOI Industry Consortium claims that planar FD-SOI technology will enable substantial improvements in performance and power consumption for next-generation mobile devices, delivering high-performance applications with rich multimedia and communications functionality, reduced power consumption, and improved battery life.

 As system-on-a-chip (SoC) designs increase in complexity to deliver the enhanced features required by today’s mobile consumer, designers face the challenge of continuing to reduce the voltage while maintaining the stability of the static random access memory (SRAM) bit-cells. Early benchmarks on FD-SOI technology demonstrate the ability to reduce the SRAM operating voltage by 100 to 150 mV, thereby reducing memory power consumption up to 40% while maintaining the stability of the SRAM. Using an ARM Cortex processor as a prototyping vehicle, a team of SOI Industry Consortium members demonstrated that planar FD-SOI technology enables designers to continue to decrease the voltage to reduce the overall power, while maintaining system performance.

 FD-SOI may also improve system performance as designers transition from generation to generation.  Traditionally, low-power manufacturing technology processes from one generation node to another yield a performance gain ranging from 20% to 30%. This assessment indicates that when the same transition also includes FD-SOI technology an additional 80% gain can be achieved beyond the traditional increase.

 This level of improvement can enable higher-performance handheld products while significantly reducing the overall system power, which translates into a superior user experience. FD-SOI also provides a compelling manufacturing advantage compared to other potential solutions. Due to its advanced starting substrate, FD-SOI wafer processing is simpler for the chip manufacturer. The elimination of a considerable number of mask layers during transistor-formation processing drives simpler manufacturing process flow, and thereby a cost-efficient approach to further shrinking CMOS transistors.

SOI Industry Consortium

Related Articles