ST researchers demonstrate fully integrated RF front-end at ISSCC ‘05

Among 12 papers being presented by STMicroelectronics researchers at next week's International Solid-State Circuits Conference (ISSCC) in San Francisco, Calif., the most notable presentations will cover advances in digital video broadcast and RF integration in 3G applications. In the field of above-IC integration, ST researchers in partnership with the CEA (French Atomic Energy Commission) and CSEM (Swiss Center for Electronics and Microtechnology) laboratories will demonstrate the feasibility of a fully integrated RF front-end for wideband CDMA applications using above-IC bulk acoustic wave filters. Designed and fabricated in a 0.25-micron BiCMOS technology that is enhanced with above-IC capabilities, this experimental chip is the first application of a filter on top of an IC. The above-IC approach dramatically reduces the number of external components and total board area in the mobile terminal, which results in shorter product development cycles and lower manufacturing costs.

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The session on wireless receivers for consumer electronics has invited ST´s research center in Crolles, France, to introduce a complete digital video broadcast-T tuner, fabricated in a 120-nm CMOS technology on a single chip. ST’s solution unveils novel approaches to overcoming CMOS intrinsic limitations (1/f noise, low supply voltage), including an original charge-pump design. This paper clearly points to a new trend in digital terrestrial and satellite TV tuners, where the complete system-on-a-chip (SoC) integration in standard CMOS minimizes the overall bill of materials.

In baseband processing, ST will report on two implementations of the second-generation satellite digital video broadcast (DVB-S2) codec. The added LDPC (Low-Density Parity Check) and BCH (Bose-Chaudhuri-Hocquenghem) codes enhance the error correction rates and approach the theoretical performance limit in the 130-nm CMOS version. The second test chip, built in low-leakage 90-nm CMOS, offers faster operation (300 MHz) while using fewer blocks of custom high-speed memories. This kind of error correction coding holds a promising future for wireless LANs or any other high-speed digital communication in noisy environments, said STMicroelectronics.

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