High speed demultiplexer comes with latched comparator input

Inphi Corporation has released a high speed1:8 demultiplexer with latched comparator input operating at bit rates from DC to 12.5 Gbps.  A member of its high speed logic family, the 1385DX, with its high sensitivity latched comparator input and auto-synchronizing demultiplexer, enables test and measurement, defense, and aerospace designers to develop high speed data acquisition front ends and to deserialize high speed signals.

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The 1385DX features a high-speed sampling clock and high-bandwidth latched comparator input that can be used to sample high-bandwidth analog signals and demultiplex them to a lower data rate for post-processing via a low speed FPGA or ASIC.  Additionally, the high bandwidth input supports digital signals up to 12.5 Gbps, which are latched and deserialized to an 8-bit parallel output bus.  The 1:8 deserialization, coupled with an on-chip synchronization circuit and adjustable output levels, allow the use of multiple demultiplexers in parallel, with automatic alignment of the parallel output buses of the demultiplexers.

 The 1385DX accepts a single external clock at up to 12.5 GHz that samples the input signal from the high-bandwidth comparator.  Internally generated clocks are used for demultiplexing the latched input signal to an 8-bit parallel data bus.  The device outputs a full-rate clock (⅛ of the input clock) or half-rate clock (1/16 of the input clock) as determined by the CLKSEL input.

The demultiplexer’s built-in synchronization circuit allows two or more 1385DXs to be automatically synchronized using a master/slave mode, in which the slave demux synchronizes to a signal (CK16) from the master, or a slave/slave mode, in which both 1385DX’s are synchronized to an external master clock (1/16 of the input clock frequency).  Synchronization occurs within at most 152 periods of the input clock.

The 12.5 Gbps 1:8 demultiplexer with latched comparator input operates from a standard +3.3 V power supply.  Currently, it is shipping in pre-production quantities in an 8 x 8 mm QFN package or on an evaluation board with SMA connectors. Full production is expected to begin this quarter.

Key features and benefits: 


Feature

Benefit

Supports clock rates up to 12.5 GHz

Maximizes system bandwidth

Low deterministic (10 ps pp) and random jitter (2 ps rms), and fast rise and fall times: 75 ps

Clean clocks and wide-open data eyes alleviate layout design constraints

Automatic synchronization of multiple 1385DX demultiplexers

No additional external components to align phases of multiple 1385DX parallel data buses

Differential CML outputs with common mode adjust and 500 mVpp differential amplitude

Make direct connections (no external components) to low-power FPGAs

High-sensitivity latched comparator input with front-end bandwidth of 14 GHz

Sample multi-GHz signals with greater accuracy

www.Inphi-Corp.com/product-overview/ghz-logic.php

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© 2012 Penton Media Inc.


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