Fully integrated systems-on-a-chip (SoCs) represent a key trend in mobile device design. Separate processors are giving way to multiple embedded cores, including cores for DSP operations. In handsets, DSPs are widely used for filters as well as for voice and video compression and decompression operations.

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Leading this trend, the 1-GHz CEVA-X1643 DSP core from Ceva Inc. is designed to boost overall chip performance for a broad range of applications, including wireless and wireless communications, surveillance, and portable multimedia. It takes advantage of the architectural efficiency and mature software development environment of the company’s existing CEVA-X family of DSP cores.  

The CEVA-X1643 improves on its predecessors with support for an advanced data cache and tightly coupled memory architecture, which streamlines software integration and software porting from other DSP platforms and reduces overall time-to-market. It also provides memory management support, simplifying the real-time operating system (RTOS) and multi-tasking.

The core’s integrated power scaling unit (PSU) enables a highly energy-efficient architecture. Also, its configurable 64/128-bit AXI system busses support high memory bandwidth. The core additionally provides inherent support for seamless migration from Texas Instruments’ C6x C-code. It boasts more than 1-GHz DSP performance using standard 40-nm process technology at worst-case conditions. And, it’s fully compatible with all CEVA-X products.

The CEVA-X1643 DSP produces a significant performance boost, combining a very long instruction word (VLIW) architecture with single instruction multiple data (SIMD) capabilities. Its 32-bit programming model supports a high degree of parallelism, including the ability to process up to eight instructions and 16 SIMD operations per cycle. With a well-balanced pipeline, it can surpass 1 GHz in chips implemented at the 40-nm technology node.

Further, the CEVA-X1643 uses ARM’s high-performance Advanced eXtensible Interface (AXI) memory subsystem, which supports configurable AXI bus width, parallel read and write transactions, read after write transactions, and other advanced capabilities, ensuring target performance is met in a real-life system. The use of de-facto industry standard system buses together with a fully cached CEVA-X processor enables high performance, a shorter design cycle, and easy integration into the target SoC.

The core’s innovative PSU provides advanced power management for both dynamic and leakage power. The core supports multiple clock sources and power domains associated with the main functional units, such as the DSP core and the instruction and data caches. The PSU supports multiple operational modes ranging from full operation, debug bypass, and memory retention to complete power shut-off (PSO).

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