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While nanometer technology enables more functionality on one chip, it also brings several new physical effects that must be accounted for in simulation and modeling. This is especially true when integrating digital, analog and RF circuitry in a single systems-on-chip, a daunting task to say the least. Traditional verification and extraction tools have limitations, especially for simultaneously examining and validating digital and RF components. In addition, the latest standards in RF design, such as 802.16, and the design of multimode chips, such as global system for mobile communications (GSM), global positioning system (GPS) or Bluetooth, make it increasingly difficult for RF designers to meet specifications.

Fortunately, developments in complementary metal oxide semiconductor (CMOS) manufacturing technology help overcome RF integration barriers by moving RF processing into the digital domain.^[1] As RF CMOS technologies move to smaller feature sizes, it's becoming more feasible to design using this technology because of increased device performance. The performance capacity of silicon germanium (SiGe) BiCMOS devices at 0.25 µm (90 GHz) is the same as the performance capability of RF CMOS devices at 0.13 µm^[2]. The increased performance in standard CMOS processes allow RF designs to be transitioned to standard CMOS processes. This has the benefit of having larger manufacturing volumes available and the ability to integrate RF blocks with digital blocks on one chip.

But with these smaller technologies come a host of physical effects that must be modeled. With finer line widths and longer interconnect comes increased parasitic resistance. The use of copper introduces dishing and erosion effects, which cause the metal layers to sag in the middle and to become dependent on spacing to other conductors. The trend to design at higher frequencies is increasing the importance of parasitic inductance. Smaller technologies result in lower yield, which increases the need for yield improvement techniques such as via doubling. All of these new effects need to be modeled accurately to ensure first silicon success.

For system-on-chip designs, RF designers no longer have the luxury of using multiple re-spins to fix design problems. With nearly half of all mixed-signal designs failing first silicon^[3], and with mask costs in the $1 million range, it's important to do as much verification as possible to prevent re-spins.

Challenges in first silicon success

Challenges in RF design, such as meeting tight standards, the large number of re-spins required, and difficulties in parasitic extraction make it difficult to achieve the goals of having a low-cost, low-power solution with a small form factor. It is typical for an RF project to have several re-spins built into the schedule. This increases the time to market and the cost of the project.

RF standards are often difficult to meet. To trade off between phase noise, gain and insertion loss, distortion, power output, and image rejection, it becomes necessary to explore different architectures using accurate simulation, accurate device models and accurate parasitic extraction. But parasitic extraction is often done using hand calculations. Because of these hand calculations, some capacitance effects may be missed. Resistance of complex shapes is often difficult to calculate by hand, as it is based on current flow direction, which may be difficult to calculate for complex shapes. Operating at higher frequencies increases the importance of measuring parasitic inductance, which is also difficult to calculate by hand.

Solutions for accurate nanometer silicon modeling

Comprehensive silicon modeling can help to identify and improve signal and noise problems, and to handle inductive effects unique to RF designs. A silicon model consists of two parts: device models and interconnect resistance, and capacitance and inductance (RLC) parasitics. Having an accurate silicon model will enable designers to model how their real silicon will behave when manufactured, reducing the risk of re-spinning the chip, and increasing the chance that the chip will still meet specifications when manufactured.

Successful RF design requires careful attention to both intentional device models, such as transistor and spiral inductor models, and accurate parasitic extraction for the interconnect. The addition of inaccuracies from parasitic resistance, capacitance and inductance can cause degradation to the design specifications.

Figure 1 shows a typical design flow. First, the specifications are decided on and the technology process is chosen. With this technology-specific information, such as model files, device generators, and design kits, the designer can start doing the RF circuit design. An architecture is chosen for the circuit, and schematic capture and simulation are done. The parameters for the transistors and the capacitance and inductance values are optimized and tuned to make sure that the specifications are met. When the designer is satisfied with the trade-offs made between noise figure, gain/insertion loss, distortion, phase noise, image rejection, linearity and power output, the layout engineer will hand-layout the design. At this point, design routing code (DRC), layout vs. schematic (LVS) and extraction are done. This is where the silicon model gets created.

A silicon model consists of two parts. The first part is created by LVS. This includes device recognition, and measurement of device parameters, such as width (W), length (L), area of source and drain (AS/AD), and the stress effect parameters length of diffusion area (SA, SB and LOD). These measured parameters such as W, L, AS/AD, SA, SB and LOD then get fed into the transistor model. The second part of the silicon model is the interconnect model. Resistance, capacitance and inductance are calculated for the interconnect. This includes both the intrinsic values between the metal and the substrate, and the cross-coupling values between two nets. This silicon model is then re-simulated, and there is a performance evaluation where it is decided whether the modeled circuit still meets specifications. If not, then the circuit needs to iterate and be re-tuned and re-optimized. If the circuit is performing correctly, then the block is ready to be integrated with the other blocks in the design.

In a traditional flow, LVS only measures W and L, and only RC extraction is done. An improved flow will measure advanced parameters such as AS, AD, SA and LOD in the LVS stage. These advanced parameters are then passed to the transistor model. In addition to doing RC extraction, in the new flow, inductance extraction is also performed, as well as advanced extraction for effects not included in transistor models, such as vias, gate polysilicon, contact to polysilicon capacitance, and diffusion resistance. Advanced extraction also includes extracting the effects of metal fill and taking in-die variation into account.

Advanced parameters in device models

When focusing on the first part of a silicon model, which is the device recognition and parameter extraction portion, it is important to recognize that it is usually not sufficient to assume that the layout engineer will lay the circuit out exactly as specified by the circuit designers. Two examples will be used for this: a spiral inductor and a CMOS transistor. An inductor in the layout is assumed to have parameters that match those in the schematic. But if the designer has added coils, or turns, to that inductor in the layout, it will not only change the device parameters, but will also affect the performance on the chip. See Figure 2. In this example, the layout engineer needed to connect the left terminal of the inductor to the top right, thereby adding an extra part of a turn. If the change is made without also modifying the parameterized cells, simulation will not be accurate. Manufacturing a chip with inaccurate simulations will more than likely result in costly re-spins.

If the silicon model created doesn't include the real extracted parameters, the silicon model will not represent how the manufactured silicon will behave. This method of device extraction and comparison is not a true verification; instead, the model parameters are being compared to themselves. The only way to determine that the physical layout is equivalent to the model is to actually extract and measure the physical parameters in the layout. These physical parameters can then be compared to the parameters in the model to ensure that what is being built is indeed what was simulated and vice versa.

Parameterized cell comparison methodology is commonly employed because it is difficult, if not impossible, for most LVS tools to properly extract the physical parameters. However, for relevant simulation, it is important to not only know the basic parameters such as length and width of transistors and other devices, but also the more unique or difficult-to-measure parameters needed for accurate simulations. An example of this is the diffusion area of a MOS device. Simulation of diffusion gives designers an accurate picture of power and reliability — how long the device will perform before it “stresses.” Transistor models such as BSIM4 for CMOS devices not only take the width and length into account, they also accept the area of the drain and source region (AD/AS) and the length of the diffusion area (SA/SB/LOD). If the default values are used for AD, AS, SA, SB, and LOD, the simulation results will be inaccurate. An example is shown below in Figure 3. In this example, the layout engineer has reduced the drain parasitic resistance by extending the drain region and adding more contacts while maintaining the width and length of the transistor. The AD value has increased from 12 to 13.4, which will affect the simulation results.

Therefore, to have an accurate silicon model, designers require a robust LVS tool that recognizes standard devices, then goes deeper, measuring the device turns, wire space, width, length, and the area of the source and drain regions, until all physical parameter data are mined. These parameters will then be accurately passed to the device model for accurate simulation.

Resistance, capacitance and inductance extraction for copper processes

The second portion of the silicon model is interconnect parasitic extraction. With the migration to copper as the main metal for the newer RF CMOS processes, there are more challenging considerations in modeling. There are several reasons that the industry is moving toward using copper metallization and low dielectric constant (k) dielectrics instead of aluminum metallization and silicon dioxide. First, copper decreases resistivity, as the resistivity of copper is 1.7 Ohm-cm compared with 3.0 Ohm-cm for aluminum. This provides almost a 40% reduction in parasitic resistance as compared with aluminum. Second, with smaller geometries, cross-coupling capacitance is increasing, which increases the amount of crosstalk. To reduce this, a lot of research is done in creating lower-k dielectrics that work with copper processes.

One of the effects caused by copper processing is in-die variation (height of conductors that vary across a chip). At earlier process nodes, fixed-cross sections could be assumed. Finite dimensions were norm and height was fixed, as sheet resistance was consistent for each interconnect layer. But when copper processing and 130 nm process technology converged, cross-sections were affected, causing trapezoidal cross-sections and dishing. The cladding material used with copper processing has a different resistance effect than copper; that resistance is a function of width and spacing of conductors. The foundry must now inform designers how critical dimensions will vary so that compensations can be accounted for in the design phase.

Lastly, parasitic inductance is becoming increasingly important, as smaller technologies allow designers to design at higher frequencies. With frequencies above 500 MHz, it's important to measure parasitic inductance because the impedance is proportional to R + jωL. As increases, the contribution of parasitic inductance increases compared to parasitic resistance. Also, with parasitic resistance and capacitance decreasing, inductance is becoming a more prominent component in impedance. Parasitic inductance can also cause impedance mismatch for RF designs, which can significantly degrade the overall system sensitivity.

Next we will show the creation of an accurate silicon model using Calibre LVS/xRC/xL in the design of an LC differential oscillator.

LC differential oscillator

Figure 4 is a schematic of a voltage-controlled oscillator (VCO), which is one of the main blocks in modern communications systems. Frequency upconversion and downconversion is mainly done by VCOs and mixers in transmitter and receiver front ends. A VCO's noise affects the noise performance of the entire transceiver, so it is important to decrease the VCO's phase noise as much as possible. For designing a tuned VCO, a lower-Q resonator is used, which allows for a higher tuning range. The varactor is used to change or tune the frequency. Both parasitic extraction and accurate device parameters and models are important to having accurate simulations for VCOs.

The LC differential oscillator in Figure 4 was designed using a six-metal layer 0.18 µm process. Figure 5 shows the layout of the oscillator.

Effects of parasitics and device parameters on LC differential oscillator

First, we'll look at the frequency of oscillation vs. the control voltage. Simulations were done using Eldo RF, and parasitic extraction was done using Calibre xRC and Calibre xL.

The frequency of oscillation is determined by:

Parasitic capacitance and inductance directly affect the oscillation frequency.

Figure 6 show the simulation results with the ideal circuit with no parasitics, then shows how the graph shifts with the measurement of AS and AD for the transistors, and with the addition of parasitic capacitance, resistance, and inductance.

Phase noise is also affected by parasitic effects. Phase noise is defined as the normalized frequency domain representation of random phase fluctuations. It is evaluated to be the power spectral density (1 Hz bandwidth) in one modulation sideband referred to the carrier power.

As shown in Figure 7, the phase noise increases as parasitic resistance and capacitance are taken into consideration. When parasitic inductance is added, the phase noise improves. This is because the amplitude of the output depends on the Q factor, the inductance value and the bias current. Because Q factor and the bias current are constant, and the inductance value is increased by the parasitic inductance value, parasitic inductance is the main value that causes the carrier power to increase, decreasing the phase noise. This example shows that it is important to include advanced device parameters, as well as advanced parasitic extraction to see the effects of the parasitics on your design specifications.

Conclusion

Trading off among power, noise, linearity, gain and frequency of operation requires the use of an accurate silicon model, which includes accurate models for intentional devices such as transistors and spiral inductors. It also requires an accurate interconnect parasitic model, which takes via capacitance, gate polysilicon to contact coupling, planarity fill, antenna effects, copper processing issues, and parasitic inductance into account. This allows the designer to accurately model as many of the physical effects as possible. The parasitic resistance, capacitance, and inductance in this LC differential oscillator caused the frequency to shift by 9.2%. The increased area of the source region caused the frequency to shift by 0.4%. This shows that it is important to have both accurate device models with real measured device parameters and accurate RLC extraction to accurately model how the silicon will behave when manufactured.

By implementing an advanced silicon modeling flow, designers can account for the complex device and interconnect issues that so profoundly affect the accuracy of analysis and successful manufacture of a design.

References

1. Krenik, B., Frantz, G. “Digital RF Techniques Ease Chip Integration Challenges,” Eedesign.com, Oct. 15, 2004.

2. Silicon Germanium Semiconductors: The Need for Speed, Semico Research Inc.

3. Collett International, 2001 IC/ASIC Design Closure Study.

ABOUT THE AUTHOR

Karen Chow is a technical marketing engineer at Mentor Graphics in Wilsonville, Ore. She received her Bachelor of Science degree in electrical engineering from the University of Calgary in 1994. She has 10 years of work experience in the telecommunications and EDA industries, focusing on analog IC design and parasitic extraction. Chow can be reached at karen_chow@mentor.com.