Existing 2G and 3G basestations and infrastructure were designed for voice service. As data usage has become common, carriers are updating their systems to handle the ever-increasing load of video and other data traffic inside limited frequency spectrum. New basestation equipment is desperately needed to keep up with current demands, but it also must be scalable as data usage rises.

The new mobile standards are implementing higher data rates with advanced baseband processing techniques such as adaptive beam forming, adaptive modulation, multiple-input multiple-output (MIMO) antenna systems, space-time coding (STC), and digital RF processing like crest factor reduction and digital pre-distortion. One of the best ways to incorporate those techniques into basestations, from femtocells to macrocells, is to use the Transcede wireless baseband processors from Mindspeed Technologies.

The Transcede T4000 and T4020 have the performance necessary to meet the huge increase in basestation computational complexity caused by the migration from a voice-centric 2G/3G mobile network to a data-centric 3G+/4G mobile network (see the figure). These chips combine a complex set of general-purpose DSPs plus FPGAs and networking processing units (NPUs). Manufacturers can now build scalable platforms for picocell and macrocell applications that leverage the same Transcede device and Mindspeed’s scalable software architecture.

The Transcede systems-on-a-chip (SoCs) integrate 22 processing elements into a single device, including two ARM Cortex A9 multicore symmetric multiprocessing (SMP) reduced instruction set computer (RISC) processors, 10 CEVA DSPs, and 10 DSP accelerators that support the complete WCDMA, Long-Term Evolution (LTE), or WiMAX (Layers 1, 2, and above) processing needs of single- and multi-sector basestations. Transcede can deliver three sectors of LTE processing in a single device while still providing substantial processing headroom, allowing manufacturers to deploy their own value-added features. And all this can be done with significantly lower power consumption.

“Manufacturers have re-architected their existing 2G and 3G basestations to support mobile broadband technology field trials and are now looking at more integrated solutions to help cost- and power-reduce their 3G+ and 4G basestation designs, which currently cost about $1000 per blade using multiple DSPs, FPGAs, and other components and consume 100 W of power,” said Alan Taylor, director of marketing for Mindspeed’s Multi-Service Access business unit.

“Transcede devices can cut power consumption to less than 15 W for sub-$250 blades with significantly better performance, lower complexity, simplified programming and scalability, and a smaller footprint. Transcede SoCs will help redefine wireless infrastructure economics during what is expected to be a major basestation upgrade cycle,” Taylor added. 

The Transcede family can be used to develop 4G equipment for LTE-FDD, LTE-TDD, and WiMAX 802.16d,16e, and 16m, as well as 3G W-CDMA NodeB systems (spanning WCDMA, HSPA, and HSPA+ requirements). The family’s scalable hardware architecture enables the same software to be used for picocells, microcells, and macrocells, as well as future low-cost femtocell designs once industry standards and product requirements solidify.

The devices include the very latest Cortex A9 multicore SMP RISC processors from ARM Ltd., coupled with the latest DSP processors from CEVA. Integrated Layer 1 and Layer 2 processing reduces system latency compared to solutions that split physical-layer (PHY) and media access control (MAC) processing between discrete network processors, DSPs, and/or FPGAs.

The devices also include built-in hardware accelerators for fixed functions including filter processing and forward error correction. Additionally, they integrate other key system features to further reduce system costs, including complete I/O functionality for concurrent use of both CPRI/PCI Express and sRIO interfaces, plus IEEE 1588 version 2 clock-recovery support for network timing and synchronization, and a built-in ciphering engine both for the radio interface and to support all-IP backhaul networks.

Mindspeed’s single-threaded programming model was developed specifically for multicore SoCs with complex DSP arrays. It enables manufacturers to use standard C programming tools to add proprietary value in areas like interference mitigation, beamforming, and channel estimation, fully decoupled from the underlying hardware to enable software portability and simplified maintenance. Embedded trace capture provides complete visibility into program flow, allowing for non-intrusive real-time debug and optimization.

The Transcede devices can use the same open software architecture across many family members with different price and performance points. The family supports all required 2G, 3G, and 4G air interface standards. Also, software developed on one Transcede device can be ported to other family members across the full range of system platforms, including femtocell, picocell (indoor and outdoor), microcell, and macrocell basestations, as well as remote radio heads.

The processing cores are optimized for power efficiency and proven in wireless handset applications. Additionally, built-in power-management capabilities clock down processing operations to reduce power consumption during low-traffic periods.

The family debuts with the T4000, whose processor cores run at 600 MHz with 12-W power consumption, typical, and the T4020, with 750-MHz processor cores and typical power consumption less than 15 W. The T4000 supports LTE or WiMAX Layers 1 and 2 processing needs for three sectors of 10 MHz for 2x2 MIMO antenna systems. The T4020 performs similar Layer 1 and 2 processing for up to three sectors of 20 MHz for 2x2 single-input multiple-output (SIMO) antenna systems.

A complete reference design supports all of the Transcede devices to accelerate time-to-market schedules. The reference design includes a Linux board support package and standard PHY implementation for LTE, WiMAX, and W-CDMA with associated utilities and test scripts.

The T4000 and T4020 are available in sample quantities. Volume production is scheduled to begin in the third quarter of 2010. The devices are packaged in a 31- by 31-mm high-performance flip-chip ball grid array (HFC-BGA). The T4000 costs $200 and the T4020 costs $250, both in OEM volumes of 10,000 units.