STMicroelectronics' 45 nm CMOS design platform with multiple threshold transistors cuts the silicon area by half compared to designs implemented in 65 nm technology. At the same time, the process improves speed by up to 20% or reduces leakage current by half while in operation, and, in retention mode, reduces leakage current by several orders of magnitude.

The 45 nm design platform is fully supported by CAD tools from Cadence, Mentor Graphics, Synopsys and Magma. Customers can immediately begin designing advanced SoC solutions using familiar industry-standard tools.