CMOS NAND flash occupies less real estate than earlier version

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Toshiba America Electronic Components has developed a 16-Gb NAND flash memory chip, fabricated with 43-nanometer process technology. It was co-developed by SanDisk Corporation of Milpitas, Calif.

The new 16-Gb products have a chip area of 120-square millimeters, 70 percent less than NAND-flash memories fabricated with 56-nm process technology. Memory cells are grouped and controlled in NAND strings of 64 cells aligned in parallel — double the number of 56-nm devices — with a dummy word line at either end to prevent program disturbance.

This technology contributes to reduce the number of select gates and to improve memory area efficiency. Modification of the peripheral circuit design has also contributed to reduced chip area. The addition of high-voltage switches to the circuit reduces the number of control-gate driver circuits required to drive word lines, and ground buses are routed on the memory cell arrays.

Toshiba has begun shipments of commercial samples of the 16-Gb, single-chip, multilevel cell NAND flash memories and will begin mass production in March. The company intends to start mass production of 32-Gb NAND flash memories early in the third quarter of this year.

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© 2012 Penton Media Inc.


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