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The U.S. Department of Defense (DoD) is the largest user of test equipment in the world. The diverse technology being tested in aircraft, ships and communication systems creates unique demands on test equipment. For example, many of these test systems are deployed in rugged field environments and have to be supported and maintained for 20 to 30 years. The DoD plans to meet next-generation test system challenges with a technique called synthetic instrumentation (SI), also commonly known as virtual instrumentation^[1]. A report to Congress from the DoD Office of Technology Transition in February 2002 stated, “A single synthetic instrument can replace numerous single-function instruments, thereby reducing the logistics footprint and solving obsolescence problems.”^[2]

Among the potential applications for this technology, SI can be used effectively for testing Joint Tactical Radio System (JTRS) communication devices, providing a reduced footprint, faster throughput, and lower cost. JTRS is a U.S. military initiative to develop a family of software-programmable and modular communications systems that will become the principal means of communications for soldiers on the digital battlefield. All waveforms, protocols, encryption, and communications processes will be implemented in software-defined radio (SDR) technology.

The DoD has created a standards body called the Synthetic Instrument Working Group (SIWG), whose role is to define standards for interoperability of synthetic instrument systems. The SIWG defines a synthetic instrument as, “a reconfigurable system that links a series of elemental hardware and software components with standardized interfaces to generate signals or make measurements using numeric processing techniques.”^[3] Engineers can reconfigure the hardware building blocks (that is, ADCs and processing elements) of a synthetic instrument through powerful application software to make application-specific measurement systems.

Enabled by recent advances in bus architectures and semiconductor devices, SI-based systems provide design and test engineers in military electronics open access to the raw data so that they can create any measurements they need in software. Three key technologies driving advances in SI are data buses, processors and reconfigurable processing.

Exploiting PCI Express bandwidth

Because SI systems use processing elements that are separate from the measurement or stimulus devices, data bus bandwidth determines the types of applications that can be met through the open approach of SI. This is an important consideration because the bus limits the data rate that can be streamed from the device to the processing element. The emergence of the high-throughput PCI Express bus expands the range of potential applications to include high-channel count, high-throughput, or multimodule applications such as IF high-speed data recording and playback, mixed-signal test, or image acquisition.

For most synthetic instruments based on PCI Express, bus bandwidth exceeds signal bandwidth (BW_BUS > BW_SIGNAL), so you can send the entire waveform from the device to the processing element. The real power of this architecture is that you can customize your application, in addition to getting the final results. When the signal bandwidth is greater than the bus bandwidth (BW_SIGNAL > BW_BUS), these applications are typically solved with non-SI devices by using large amounts of onboard memory or vendor-defined firmware for onboard processing.

PCI Express meets the needs of SI systems because it delivers the highest throughput of any commercial communications bus. PCI Express maintains software compatibility with traditional PCI, but replaces the physical bus with a high-speed (2.5 Gbps) serial bus. PCI Express is available in 1x, 4x, 8x, and 16x links, and provides 250 Mbps of throughput per lane with very low latency. The 1x and 4x options, most commonly used for instrument class hardware, provide 250 Mbps and 1 Gbps (four lanes at 250 Mbps) of dedicated throughput, respectively. The 16x link, which provides 4 Gbps of throughput, is commonly used in new PCs for plug-in video cards.

Because PCI Express is a serial bus, it is well suited to cabled interfaces. Cabled PCI Express is a standard cabled version of PCI Express used for high-performance interconnects of system components. For example, cabled PCI Express is currently used to connect a host PC to a PXI chassis with sustained transfer rates of nearly 800 Mbps. You can also use cabled PCI Express as the interconnect between a PXI system and a RAID array of hard disks for high-speed data recording and playback applications. The SIWG identified the cabled PCI Express standard as the high-speed data bus for SI systems, as shown in Figure 1.

PXI is an industry standard hardware platform for virtual/synthetic instrumentation that was introduced more than 10 years ago. The latest PXI specification, PXI Express, integrates the PCI Express bus, enabling PXI to solve many new military/aerospace applications. By integrating PCI Express into PXI, PXI Express increases bandwidth by 45 times, integrates highly accurate timing and synchronization, and preserves compatibility with existing software and more than 1500 existing PXI modules (Figure 2).

With up to 6 Gbps of total system bandwidth, PXI Express can stream the data to or from the host for performing software-defined measurements and modulation. This is useful because it provides the flexibility to change the software to generate entirely different types of modulated stimulus signals or different classes of measurements. Also, this system can be used as a software-defined radio to prototype a real-world communication system. A block diagram of the actual hardware modules and software is shown in Figure 3.

Multicore processors

While transferring signals from high-speed I/O hardware to the PC with the increased throughput of PCI Express, the PC must have enough processing power to process all of the data transferred on the bus. Moore's Law has long been a familiar way of talking about the continual increase of performance in processors. The prediction that the number of transistors on an IC will double every 18 months, thus implying a corresponding increase in processor performance, has held true since the 1970s. However, Moore's Law is now at a turning point.

The previous approach of just improving the clock speed has introduced challenging power and cooling issues. The latest advancement in processor technology is to place multiple cores, or computing engines, within a single processor to handle increased processing through a parallelized approach. Currently, Intel and AMD have released dual-core processors, and future processors will expand the number of cores to four or more. In fact, Intel is targeting to deliver an 80-core processor by 2011.^[4] Multicore-processing technology provides the processing performance needed to meet demanding SI applications.

To benefit from the improved processing performance of multicore technology, however, engineers must be able to program their test code to target the different cores. Writing multithreaded applications in text-based programming languages, such as C, is non-trivial and requires expertise in the semantics of creating and managing the threads and passing data between them in a thread-safe way. Alternatively, users can take advantage of higher-level abstractions to handle the parallelization of code to target multiple cores. Graphical programming tools, like NI LabVIEW, are inherently parallel and can automatically generate programs optimized for multiple cores. In LabVIEW, two loops that do not share a data dependency automatically execute in separate threads (Figure 4).

Consider Table 1 for a representative example of the performance improvement achieved with an existing LabVIEW application on a dual-core processor vs. a single-core processor, like the 2.16 GHz Intel Core 2 Duo T7400 dual-core processor used in the new NI PXIe-8106 embedded controller. Through LabVIEW, engineers can take advantage of existing code on multicore processors to enhance the performance of their test applications

FPGA processing

For the most demanding processing applications, synthetic instruments will need to exploit distributed processing. One of the most promising technologies in this area is the field-programmable gate arrays (FPGAs). Through FPGAs, you can define the behavior of the hardware and perform in-line processing or distributed processing on the device, as shown in Figure 5. In addition, FPGAs provide faster execution because they are inherently parallel and deliver deterministic (reliable) execution.

While FPGAs have been used inside of stand-alone instruments, users were not given access to reprogram them. To be useful in a synthetic instrumentation context, FPGAs must be reprogrammable by the user in software; in other words, they should be used to push software programmability down into the hardware itself. Clearly, there are advantages of performing different types of processing on a host processor (that is, dual-core processor) vs. an FPGA. For example, an FPGA is generally well-suited for in-line analysis such as simple decimations on point-to-point I/O; whereas, complex modulation might achieve better performance running on a host processor due to the large amount of floating-point calculations required.

While FPGAs offer compelling performance and flexibility for synthetic instrumentation, they are programmed through hardware description languages like Verilog or VHDL, which use low-level syntax to describe hardware behavior. Most test engineers do not have expertise in these tools. Again, system-level tools that abstract the details of FPGA programming can bridge this gap. LabVIEW, for example, can target onboard FPGAs and synthesize the necessary hardware directly from a LabVIEW program. The ideal solution for developing a distributed SI system is a single development environment, such as LabVIEW, that provides the ability to quickly partition the processing on the host or an FPGA to see which provides superior performance, as shown in Figure 6.

SDR testing requires SI systems

Harris, a worldwide supplier of tactical radio communication products, has developed the FALCON II 512 MHz multiband series of SDR communication devices. The FALCON II series includes handheld, manpack, vehicular, and base-station systems. These software-enabled devices provide ultimate flexibility to the military personnel. However, this same flexibility posed a challenge to the Harris RF test engineers because they had to create a test system that could adapt to meet the variable test requirements of each SDR. Harris RF test engineers chose PXI, LabVIEW, and NI TestStand to design a virtual/synthetic instrumentation test system that mirrored the software-defined nature of their FALCON II series devices. Figure 7 shows a simplified version of the software-defined, modular architecture that Harris implemented.

This software-defined architecture allows their testing stations to be rapidly reconfigured. For example, existing test stations can be reconfigured to support the new modulation schemes and the higher frequencies required by the forthcoming FALCON III 2 GHz communication devices. These modern test stations also delivered additional benefits, including reduced test time for each SDR and reduced footprint of each station on the production floor.

New technologies drive SI

The PCI Express bus, multicore processors, and FPGAs are three of the latest PC technologies that are enabling synthetic instrumentation. Industry-standard products such as LabVIEW and PXI Express use these technologies to enable the building of virtual/synthetic instrumentation systems. These systems will solve challenging applications that were previously solvable only using expensive and proprietary dedicated test systems.

References

1. World Synthetic Instrumentation Test Equipment White Paper, Frost & Sullivan, 2006.

2. Report to Congress on the activities of the DoD Office of Technology Transition, February 2002.

3. SIWG Meeting No. 2 Statements and Definitions, Dec. 11, 2004.

4. Intel pledges 80 cores in five years, http://news.com.com/2100-1006_3-6119618.html, Tom Krazit, staff writer, CNET News.com, Sept. 26, 2006.

Table 1. Processor performance comparison.

Benchmark	Time Requirement(s)		Improvement (%)
	Single-core 2 GHz	Dual-core 2 GHz
Program to find the prime numbers in the first 1,000,000 natural numbers	6.87	3.59	47.74
Program to calculate 1000 digits of Pi	3.96	3.06	22.73

ABOUT THE AUTHORS

Eric Starkloff is a director of product marketing at National Instruments. A board member for the Wireless Networking and Communications Group at The University of Texas at Austin, Starkloff has helped drive industry standards within groups such as the PXI Systems Alliance and the Semiconductor Test Consortium. Since joining NI, Starkloff has held many positions, including PXI product strategy manager, software group manager, NI TestStand product manager, and applications engineer. He received his B.S. in electrical engineering from the University of Virginia, with a concentration in communications system design.

Kevin Bisking is a senior product manager at National Instruments. He has expertise in precision instrumentation and automated test system design. Bisking has authored numerous technical articles in professional publications. Since joining NI, Bisking has held many positions, including modular instrument product manager, digital multimeter and switching product manager, and applications engineer. He holds a B.S. in electrical engineering from the University of Texas at Austin.