The Defense Advanced Research Project Agency (DARPA) has awarded Raytheon a $27.6 million contract to develop a programmable computing system based on an extremely fast, powerful and versatile chip.

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Raytheon's Morphable Networked Micro-Architecture (MONARCH) project calls for development by April 28, 2008, of a system that can alternate instantaneously between front-end (streaming) and back-end (threaded) processing through the use of IBM Cu-08 90-nanometer technology.

Raytheon Space and Airborne Systems will collaborate with the Information Sciences Institute of the University of Southern California to create an integrated large-scale system on a chip with a suite of software development tools for programs of high value to the Department of Defense and commercial applications. Besides USC, major subcontractors include IBM, Georgia Tech and Mercury Computer Systems.

"In the past, a bank of processor boards received information and another bank processed it," said Jack Kelble, president of Raytheon Space and Airborne Systems. "Now a tiny but highly sophisticated device a fraction of the size will perform both functions with unprecedented speed, power and capacity to store and process a vast amount of data."

Because of its ability to perform in a single-chip or a system-on-a-chip role, the MONARCH device reduces significantly the number and types of processors required for computing systems. In this application, it will be able to process incoming and outgoing data at the same time it is analyzing it.