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The design of base station transmitters continues to be driven by the need to accommodate the linearity and efficiency required by higher-order modulation schemes. The goal of achieving high linearity has been aided by analog and digital predistortion and feed-forward linearization techniques. It can be argued that the most important goal is to maintain this linearity while delivering the highest possible efficiency. This is because when compared to other base station subsystems, the transmitter accounts for a high percentage of overall power consumption, so reductions achieved through increased efficiency can lower electricity costs and minimize cooling requirements. To achieve this goal, designers are increasingly turning to amplifiers based on the Doherty architecture. To see why this amplifier architecture has risen in stature, it is important to understand its characteristics and their possibilities when realized in an actual amplifier.

The Doherty amplifier is hardly a household word among design engineers unless they are directly involved in amplifier design. It is also not a brand new concept, since it was first described by W.H. Doherty of Bell Telephone Laboratories, then a part of Western Electric, in 1936. Doherty created his amplifier design while looking for ways to improve traveling-wave tube amplifier (TWTA) performance.

Doherty's research produced an amplifier architecture that delivers very high power-added efficiency with input signals that have high peak-to-average ratios (PARs). In 1936, and for many succeeding years, there were few signal types that possessed these characteristics, since the modulation schemes employed in communication systems were AM and FM. Today, virtually every current and proposed wireless system produces high-PAR signals, including WCDMA, CDMA2000, and any system employing orthogonal frequency division multiplexing (OFDM), such as WiMAX and the upcoming long-term evolution (LTE) enhancement to the UMTS wireless standard.

The Doherty's inherent strengths are making it appealing when wireless base station manufacturers and wireless service providers are searching for ways to increase efficiency and lower operating expenses. As a result, over only a few years, the Doherty amplifier has become the amplifier architecture of choice for new base station transmitters. When properly designed, it can deliver efficiency increases of 11% to 14% when compared to standard parallel class AB amplifiers traditionally used in these transmitters.

Defining Doherty

The classic Doherty amplifier (Figure 1) consists of two amplifiers: a carrier amplifier biased to operate in class AB mode and a peaking amplifier biased to operate in class C mode. A power divider splits the input signal equally to each amplifier with a 908 difference in phase. After amplification, the signals are recombined with a power combiner. Both amplifiers operate during the peaks of the input signal and are each presented with the load impedance that enables maximum power output. As the input signal decreases in power, the class C peaking amp turns off and only the class AB carrier operates. At these lower powers, the class AB carrier amplifier is presented with a modulated load impedance that enables higher efficiency and gain. The overall result is an amplifier that provides an extremely efficient solution for the complex modulation schemes employed in current and emerging wireless systems.

Desirable though it may be for its exceptional efficiency, the linearity and output power of the Doherty architecture are slightly less than exhibited by a dual class AB amplifier. Recent advancements in analog and digital predistortion and feed-forward linearization techniques can dramatically reduce the Doherty's distortion, and careful device and amplifier design can minimize the reduction in linearity. What remains is to create RF power transistors that can accommodate the requirements of both the carrier and peaking amplifiers.

Amplifier operation

A good example of the Doherty architecture is demonstrated by a 900 MHz amplifier created at Freescale Semiconductor (Figure 2). This amplifier was designed for maximum power, efficiency, and gain with minimum variation across the 869 MHz to 894 MHz band under WCMDA operation. The amplifier was designed using a new output-matched LDMOS RF power transistor, the MRFE6S9205H.

The output matching of this transistor has been optimized for use in Doherty amplifiers. The transistor exhibits low Q and nearly twice the load impedance for maximum output power compared to the non-output matched case. This increased output terminal impedance and low Q enable excellent broadband performance in a Doherty amplifier with decreased sensitivity to load variation. The transistor is capable of delivering peak output power in excess of 250 W into a load impedance over 1 Ω. The transistor also maintains excellent efficiency under power back-off conditions with higher load impedance. The output match enables flat gain and phase over frequency, which makes it easy to implement in a system that uses linearization techniques such as digital predistortion.

To achieve high terminal impedance and low circuit Q, the internal output match must resonate with the output capacitance of the transistor die as shown in Figure 3. R_opt is the resistance that must be presented to the current generator to achieve maximum output power and C_O is the output capacitance of the transistor die. At the die plane, the large capacitive reactance greatly reduces the real impedance. An inductance to ground (L_shunt) will resonate C_O at the frequency of interest. The value is given in equation 1:

This topology has been realized with great success in 2 GHz transistors using bond wires from the drain of the transistor to a large MOS capacitor that acts as a dc block. However, from equation 1 it is seen that for a constant C_O, a 4x increase in L_shunt is needed to achieve resonance for a 2x reduction in frequency (f). The higher inductance necessary for 900 MHz operation can be realized by longer wires, fewer wires, or some combination of the two, resulting in a variety of engineering challenges. While an internal output match may not be necessary for smaller, lower-power RF transistors in less-demanding applications, the internal output match is a key enabling feature for large RF transistors in today's high-power, high-efficiency base-station power amplifiers.

In Figure 4, the measured load-pull contours of an output-matched LDMOS die are compared with those of a non-output matched LDMOS die with the same silicon. The output PAR is that of an IS-95 narrowband CDMA signal at a constant 50 W average output power. The peak power of the output matched device is highest when the load impedance is 1.25-j1.4 Ω, and the power of the non-output-matched device is highest at a load impedance of 0.65-j0.6 Ω. The highest power contour of the output matched device not only occurs at a higher impedance but does so over a broader region than the non-output-matched device. This makes the output-matched device better suited for use in a Doherty amplifier.

A Doherty amplifier can be considered as two static cases, even though the load is dynamically modulated. The carrier amplifier operates in class AB with two different load impedances that correspond to the carrier and peaking modes. The peaking amplifier operates in class C with its turn-on characteristics controlled through dc offsets in bias, control of the RF signal levels at the peaking amplifier interface, or both. The job of the Doherty amplifier designer is to convert these two load impedance conditions at the combiner reference plane into appropriate load conditions at the RF power device reference plane.

The power transistor's area of high performance in the impedance plane resulting from optimum output matching allows an impedance transformation network to be designed that meets the Doherty's two required broadband load impedance conditions, while maintaining performance across the frequencies of interest.

In the case of this Doherty amplifier, the summing load impedance at the combiner reference plane is 25 Ω in the carrier mode with both amplifiers functioning. When the peaking amplifier is off, the impedance presented to the carrier amplifier at the combiner reference plane is 50 Ω — a 2x load impedance modulation, which is typical.

The Doherty combiner is designed so that in peaking mode the same load impedance is presented to each amplifier. This impedance must allow each amplifier to deliver output power as close to maximum as possible without regard for efficiency. Figure 5 shows that it is possible to design a circuit-level match that provides P1dB CW output power greater than 263 W (54.2 dBm) from a single MRF6ES9205H in class AB or class C operation over a 60 MHz bandwidth.

In “carrier mode,” the carrier amplifier is fully functional while the peaking amplifier is off. The carrier amplifier's performance in this mode drives the broadband performance capability of the Doherty amplifier. Without regard to linearity, the designer must optimize the circuit for flat gain across frequency and high efficiency under the carrier-mode load impedance condition at appropriate output powers.

Figure 6 shows the trade offs in peak power capability and efficiency vs. input power for different turn-on conditions of the peaking amplifier while maintaining class AB bias for the carrier amplifier. Peak power is measured at 0.01% probability on the complementary cumulative distribution function (CCDF). The peak powers for all bias points converge to 560 W (57.5 dBm). At this power level, efficiency is greater than 50% when the peaking amplifier is biased at Vgs with 1.75 V. The Doherty circuit exhibits modulation and RF bandwidth broad enough to be linearized using digital predistortion systems. When enhanced by the effects of memory-polynomial based predistortion, the amplifier achieves 89 W (49.5 dBm) average output power and 41% efficiency at -55 dBc ACP under two-carrier WCDMA signal conditions.

Summary

The Doherty amplifier architecture has come a long way in the 70 years since it was conceived and has the potential to deliver the efficiency demanded by today's base station transmitters as well as those serving future generations of wireless networks. The Doherty amplifier is one of many designed at Freescale, which has been refining the basic Doherty concept, enhancing its performance, and developing devices best suited to meet its unique requirements for many years.

Author's note

Figures 3-6 are reprinted with permission of the IEEE from the paper: C. T. Burns, A. Chang, and D. W. Runton, “A 900 MHz, 500 W Doherty Power Amplifier Using Optimized Output Matched Si LDMOS Power Transistors,” IEEE MTT-S International Microwave Symposium Digest, Honolulu, HI, June 2007.

ABOUT THE AUTHOR

Christopher Burns received his BSEE degree from the University of Iowa and his MSEE degree from the University of California-Santa Barbara. He is currently an RF design engineer with Freescale Semiconductor working with RF power transistors for wireless infrastructure applications.