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Dongbu HiTek has announced the immediate availability of ARM low-power and speed-and-density-optimized physical IPs for designers developing CMOS chips processed at the 130-nanometer geometries. The licensed ARM Metro and SAGE-X standard libraries, including power management kits and memory compilers, support advanced chip solutions targeting battery-operated applications.

According to Jae Song, at Dongbu HiTek, customers have immediate access to the 130-nm physical IP via the ARM web site at no charge. He confirmed that the standard cell libraries maximize design freedom to extend battery life by minimizing power consumption, particularly during standby operation.

"Compared to existing design libraries that claim to improve power management, the ARM products offer more standard cells with more power consumption options," said Song. "These libraries can, therefore, optimize power use by giving fabless chip designers more freedom."

The ARM libraries offer standard cells that are about 40% smaller than those used in the earlier 0.18-micron library and the ARM Metro standard cells offer an additional 10% to 15% area reduction over SAGE-X in the 130-nm node. The ARM Metro standard cell library includes power-management kits that enable dynamic and leakage power-saving techniques such as clock gating, multivoltage islands and power gating. Accordingly, the migration to 130-nm processing paves the way for yielding more useful chips per wafer.