For a PDF version of this article, click here.
As higher frequency sampling becomes increasingly common, the front-end design of high-speed analog-to-digital converters (ADCs) has become a crucial element of receiver design. Many applications are migrating to super-Nyquist sampling in order to eliminate a mix-down stage in the system. Amplifier performance poses a problem at these frequencies, and their inherent noise will degrade the ADC's signal-to-noise ratio (SNR) at any frequency. A transformer provides the designer with a relatively easy solution that resolves the noise issue, while providing a good coupling mechanism for high-frequency inputs.
Figure 1 shows the 14-bit, 80 Msps AD6645, which has a differential input impedance of 1 kΩ. The 33 Ω series resistors provide isolation from transient currents in the input circuit of the ADC. The resistive combination in the transformer secondary is effectively in parallel with the 58 Ω resistor. The choice of termination resistor depends on the desired input impedance. In this case, 501 Ω was chosen to match the 50 Ω analog input.
This is a simple example because we assume that the input frequency is in baseband or first Nyquist zone. The situation is quite different, however, if the front-end is called on to handle a 200 MHz analog input. What happens in the transformer? With such a high frequency applied, any difference in parasitic capacitive coupling unbalances the secondary outputs of the transformer, with the resulting asymmetry giving rise to even-order distortions at the converter's analog input. This, in turn, leads to second-order harmonic distortion in the digital signal.
To illustrate this point, Figure 2 shows the voltages on the secondary when a 2 V p-p sinusoidal input is applied to the primary. The secondary outputs are expected to produce 1 V p-p sine waves. In reality, their amplitudes differ by 38 mV p-p, with a visible phase error of 1.9°.
One way to improve the situation is to apply a second transformer in cascade with the first to provide additional isolation and reduce the unbalanced capacitive feedthrough, as shown in Figure 3.
Using this scheme, the differential voltages applied to the converter are less likely to deviate from one another, particularly at high frequencies where this matters most. Adding the second transformer reduces the parasitic coupling capacitance on the secondary of the first transformer. The second transformer in cascade enables a redistribution of the core current lost and provides more equal signals to the primary of the second transformer. The two cascaded transformers in this configuration provide a better balanced solution for high frequencies.
The performance benefit can be seen in Figure 4. Now, there is only a 0.88 mV p-p difference between the secondary outputs, with only a 0.044° phase imbalance. This is a big improvement, attained by adding one extra component.
ABOUT THE AUTHOR
Rob Reeder is an applications engineer with Analog Devices' High-Speed Converters Group in Greensboro, NC.
He can be reached at email@example.com.