Texas Instruments and Aricent have put their collective knowhow into action to create a small-cell protocol stack optimized for TI’s KeyStone-based multicore processors. As per the companies, their collaborative efforts will allow developers to more quickly, easily, and cost-effectively design small-cell basestations. The protocol stack takes advantage of KeyStone architecture elements for layers 2 and 3 as well as transport processing with Aricent’s software components. It supports both TMS320C66x DSP generation cores and multiple cache coherent quad ARM Cortex-A15 clusters, for up to 32 DSP and RISC cores. It also includes fully offloaded, flexible packet, and security coprocessors and capacity expansion for system-on-a-chip (SoC) structural elements such as TeraNet, Multicore Navigator, and Multicore Shared Memory Controller. The small-cell protocol stack will be available in the second half of this year. For more info, visit www.ti.com/multicore or www.aricent.com.

Aricent
www.aricent.com

Texas Instruments
www.ti.com