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The need to improve RF performance by directly digitizing the analog RF signal is one of the major technology gaps that impedes the transition to next-generation software-defined radio (SDR) technology. The SDR RF architecture goal is to have all communications functions residing in the digital domain and under software control. A major technology hurdle has been the lack of a reasonable solution to take the RF signal directly from the antenna and convert it immediately into the digital domain instead of the traditional analog conversion to lower IF frequencies. Data converters based on traditional semiconductor technology are simply too slow and too inaccurate to bridge this technology gap.

A solution, however, can be found in digital superconductivity electronics (SCE). SCE features the ultrahigh-speed, high linearity and wide dynamic range needed to achieve direct digitization at virtually any frequency.

HYPRES is developing a product line of all-digital RF receivers, transmitters and transceivers that feature operating frequencies from the HF band of the radio spectrum up to 7.5 GHz (within the X band of the microwave spectrum), between 20 GHz and 30 GHz (within the Ka band of the microwave spectrum) and between 20 GHz to 44 GHz (within the EHF band of the radio spectrum). Most recently, the company demonstrated a HF/VHF all-digital RF receiver designed to directly digitize frequencies from 100 kHz to 175 MHz.

Critical SCE elements

With its demonstrated performance, the all-digital RF transceiver can be realistically considered to replace analog RF “front-ends.” The major innovation of SCE is rapid single-flux quantum (RSFQ) logic. RSFQ-based devices currently run at speeds near 40 Gbps, while experiments have yielded circuit speeds of up to 750 Gbps in the lab. The high speed of RSFQ circuitry sets it apart from conventional transistor-based electronics and is the essential element in high-speed digitization of RF energy.

In addition to RSFQ logic, the all-digital RF transceiver architecture relies heavily on ultrahigh-speed, mixed-signal data converters (both ADCs and DACs) based on SCE. These are coupled to ultrahigh-speed digital signal-processing elements to make a complete digital RF “front-end.” A typical configuration of an all-digital RF transceiver is illustrated in Figure 1.

Table 1. Summary of performance data for ADC and ADR chips (clock = 20 GHz).

Chip	Input (MHz)	BW (MHz)	SINAD (dB)	ENOB (bits)	SFDR (dBc)
ADC	4.8	39	80.5	13.1	-98.4
ADC	4.8	4.85	91.9	15.0	-1071
ADC	9.55	39	75.7	12.3	-98.5
ADC	9.55	9.7	82.6	13.4	-1041
ADC	1.0	1.0	109.2	17.8	-1131
ADC	0.4	0.4	121.9	20.0	-1321
ADR	9.85	39	74.4	12.1	-91.8
ADR	175.32	39	33.1	5.2	-58.2
1 Artifilcially narrowed bandwidth, so SFDR may be somewhat overestimated. 2 With digital LO, and Intermediate frequency = 19 MHz.

The RF signal comes in from the receive antenna and is filtered and directly converted into the digital domain (for some extreme applications, a cryo-cooled analog low-noise amplifier might also be required as a pre-amplifier). Once the signal has been directly digitized, downconversion and channel filtering are carried out in the digital domain. The receiver output, in most applications, will be implemented in standard quadrature (I/Q channels) format using dual digital decimation filters, which reduces the output bandwidth and increases the effective number of bits. Because this technique is spurious-noise-free, the effective number of bits (ENOB) is actually greater than in the original digital sample, unlike conventional devices, where the effects of spurs reduce the ENOB factor.

Following the initial very high-speed processing by the SCE, the digital data output is slowed to standard electronics interface speeds (such as 80 Msps) and handed over to conventional digital circuits like FPGAs for final processing, such as filtering, demodulation or coding. Multichannel operations are achieved with a straightforward technique that connects multiple digital downconverters and channelizers to a single ADC.

The HF/VHF all-digital receiver developed by HYPRES features a logic system capable of sampling rates of 20 Gsamples/second (Gsps) to 40 Gsps, which enables very high signal-to-noise performance. Key attributes of the HF/VHF all-digital receiver include a low-pass delta modulator optimized for the 100 kHz to 175 MHz band and a heavy oversampling technique using a 20 GHz clock. The entire digitized frequency band is digitally downconverted using a programmable digital LO to set the desired channel center frequency. The downconverter uses an external LO, a 90° phase shifter and two digital mixers to obtain quadrature baseband signals (I/Q). The resulting I/Q broadband signals are applied to two programmable low-pass digital decimation filters that set the desired channel bandwidth. The two I/Q output channels provide 15-bit parallel signals for interface with room temperature electronics, such as a modem or a digital signal processor.

The transmit side carries out similar functions in the reverse order and requires only one analog component, the power amplifier, driven by a fast DAC that directly reconstructs the RF signal.

The entire down link chain consisting of ADC, downconverter and channelizer is implemented in a single IC, as shown in Figure 2.

For the HF/VHF all-digital RF receiver, tests were conducted at various input frequencies and bandwidths to measure performance parameters such as signal to noise and distortion (SINAD), effective number of bits (ENOB) and spurious-free dynamic range (SFDR). These tests consisted primarily of demonstrations of the performance of two closely related HYPRES digitizing systems: the low-pass delta ADC, and the single-chip I/Q channelizer circuit (the ADR).

Each of these configurations involved high-speed digital sampling at 20 GHz, and exhibited the high dynamic range and linearity characteristic of superconducting circuits. A summary of the key performance metrics for the two chips is given in Table 1. (For more information on the source data and the interpretation, contact HYPRES at www.hypres.com.) These data give the dynamic range of the receiver for a given input signal and output bandwidth. For example, the ADC chip exhibited a maximum ENOB of 15, for a 5 MHz input signal and 5 MHz output bandwidth. For the ADR chip with a 175 MHz input signal and a digital mixer with a 156 MHz local oscillator, an ENOB of 5.2 was achieved for a 39 MHz output bandwidth. In general, and as expected from the nature of the ADC, higher input frequency and larger output bandwidth lead to reduced dynamic range.

The next-generation ADR, currently under development, has been shown to operate near 40 GHz clocks and accompanying performance improvements. Similar developments are under way for C-band and X-band ADRs using RSFQ bandpass ADCs. Future circuits are expected to advance to even higher sampling rates (100 Gsps to 200 Gsps) and more complex specialized DSP functions so that RF frequencies up to 50 GHz could be digitized and processed directly. Direct digitization of these very high frequencies is expected to provide tremendous benefit to defense and commercial satellite communications systems.

ABOUT THE AUTHOR

Wes Littlefield serves as vice president, business development, at HYPRES. He has decades of experience in wireless and satellite communications. He is a frequent presenter on new technologies for wireless and satellite communications and has authored numerous technical papers and articles.