CriticalBlue and Cavium Networks Inc. now support Cavium’s Octeon and Octeon II architectures within CriticalBlue’s Prism software analysis, exploration, and verification product. Software developers can use Prism to build applications on multicore Octeon and Octeon II processors. A free 30-day evaluation copy of the Prism Core PSP for cnMIPS is available at www.criticalblue.com/prism/platforms/cavium/cavium.htm.

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This release is designed to go beyond purely mapping software to multicore hardware as users can quantify the benefit of software migration to the dual-issue superscalar Octeon and Octeon II families. Users also can analyze data cache misses and pipeline stalls on a thread, function, or source line level, resulting in an ability to see the impact of such cache misses on the overall concurrent schedule.

Furthermore, users can accomplish all of this on an existing unmodified software application running on a single-core model or development board. Beyond that, experienced multicore programmers will benefit from Prism’s performance tuning and multicore software verification capabilities. A three-minute demonstration of Critical Blue’s Prism capability on Octeon is available at www.criticalblue.com/prism/platforms/cavium/media/cavium_controller.swf.

The Eclipse-based Prism embedded multicore programming system enables software engineers to easily assess and realize the full potential of multicore processors without significant changes to their development flow. It analyzes the behavior of code running on hardware development boards, virtual machines, or simulators. 

Also, Prism allows engineers to take their existing sequential code and, before making any changes, explore and analyze opportunities for concurrency. Having identified the optimal parallelization strategies in this way, developers can implement parallel structures and use Prism again to verify performance efficiency and thread-safe operations.

The Octeon multicore MIPS64 processors are designed for intelligent networking applications ranging from 100 Mbits/s to 40 Gbits/s. With one to 32 cnMIPS cores on a single chip, these software-compatible processors integrate next-generation networking I/Os along with security, storage, and application hardware acceleration for throughput and programmability for the Layer 2 through 7 processing requirements of intelligent networks.

Cavium Networks

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