RF CMOS capabilities continue to advance. And recent developments announced by IBM Global Engineering Solutions and MediaPhy take it to new heights. As it inches closer to the antenna, more and more RF front-end functions are being integrated on a single CMOS die, including the power amplifier.

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IBM Global Engineering Solutions, for instance, unwrapped a new version of 180 nm RF CMOS silicon-on-insulator (SOI) process at the recent FSA Suppliers Expo and Conference. Labeled CMOS 7RF SOI, for RF front-end integration, it is designed to enable single-chip RF solutions by integrating the multiple RF/analog functions of today's handsets, such as multimode/multiband RF switches, complex switch biasing networks, and power controllers into a single-chip solutions for mobile devices. Furthermore, the developer said that the extensibility of CMOS 7RF SOI lends itself to additional integration opportunities that could eventually include filter, power amplifier, power management and receiver/transmitter functions.

In addition, according to IBM, a major stumbling block to implementing a single chip, SOI RF front-end in CMOS is voltage surge that an antenna input must endure. The surge can occur when a user brushes, say, a nylon coat against a cell phone antenna, producing voltage spikes as high as 30 volts. CMOS technology often can't tolerate such high voltages. IBM said it solved the problem with an input that divides any surges across several layers, thereby keeping the voltage low across any individual layer.

RF front-end functions in cell phones are currently handled by five to seven chips, including at least two using gallium arsenide (GaAs) technologies. IBM claims its RF front-end will reduce costs by eliminating the need for GaAs as well as by reducing chip counts in wireless devices. IBM predicts its customers, cell phone chipset makers, will initially use its technology to reduce chip counts to two or three chips before implementing a single-chip solution.

Just a few months ago, IBM had also inked a deal with austriamicrosystems AG to give its 180 nm RF CMOS process a boost in high-voltage capability. The aim here was to blend its 180 nm RF CMOS with austriamicrosystems' 0.35 micron high-voltage CMOS to give designers 20 V and 50 V breakdown capabilities in 180 nm RF CMOS.

Speaking of RF CMOS SOI, Peregrine Semiconductor at this year's MTT-S International Microwave Symposium unwrapped a 0.25 mm UltraCMOS-based enhanced SP9T RF switch for use in multiband, multimode mobile handsets.

Likewise, eyeing the emerging mobile TV market, fabless chip developer MediaPhy Corp. based in San Jose, Calif. has unveiled a single-chip CMOS solution for the application. In fact, the developer claims that its single CMOS chip is the world's first all CMOS single-die to offer true global mobile TV capability covering DVB-H, Mobile DVB-T, ISDB-T 1-3-13 segment and T-DMB/DAB standards. In addition to unparalleled mobility, the chip features a proprietary baseband architecture that enables ultralow-power consumption, offering power savings of more than 60% when compared with current products in market today, claimed MediaPhy.

“Mobile TV will only be fully embraced if you are capable of delivering the expected quality with a low-power device, stated Terry Leeder, CEO and president of MediaPhy. Offering multi-standard capability in a single die is a significant technology advancement. Achieving such dramatic power savings in tandem with high performance and multistandard capability is something we believe will have a significant impact on the market, he added.”

Implemented in 130 nm RF CMOS process, this chip is designed from a system-level standpoint to minimize the number of external components. Consequently, components such as LNA, capacitors, inductors and all necessary memory blocks are integrated into the device to reduce the bill of material (BOM) cost and enhance system performance. Plus, the single-die monolithic design features a complex frequency-agile radio and unique configurable hardware engine-based architecture. This baseband architecture not only eliminates the need for a dedicated DSP and its program memory but also allows a very low digital clock-speed as well as the lowest always-on power.