Reconfigurable CMOS RF front-end for software radio
With the use of cellular phones surging globally, designers around the world are racing to build a mobile radio that is flexible enough to handle current and future standards. Software-defined radio (SDR) seems to be the answer, but achieving such a solution with all the attributes of cost, power and size is not trivial. While the SDR Forum is spearheading the development and deployment of SDR and cognitive radio technologies in the US, Leuven, Belgium-based research center IMEC is also concurrently moving forward on this front in Europe.
Recently, the IMEC research center had completed design and tape-out of a flexible-air-interface (FLAI) baseband platform for SDR. Capable of speeds over 100 Mbps with the ability to reconfigure dynamically using software, this baseband chip development was aimed at supporting upcoming generations of mobile devices featuring 802.11n (Wi-Fi), 802.16e (mobile WiMAX), mobile TV and 3GPP-LTE communication standards. As the RF front-end is equally challenging, the focus has also shifted to this sector. Under an SDR-front-end program, IMEC researchers are developing a cost-effective, low-power reconfigurable radio in 45 nm digital CMOS technology. This radio will have a programmable center frequency that is variable from 100 MHz to 6 GHz and a programmable bandwidth from 100 kHz to 40 MHz. According to IMEC, it should cover many communication standards, at a level of performance comparable with single-mode transceivers.
To combine its RF expertise with advanced CMOS processes, the Belgian researchers are working closely with Renesas Technology Corp. In fact, to keep the momentum going, Renesas has joined IMEC's SDR front-end program, which includes the development of reconfigurable RF ICs, analog-to-digital converters (ADCs) and approaches to digitizing future RF architectures. In fact, this program builds on scalable 130 nm RF transceiver (SCALDIO) published last year in ISSCC 2007 and advances in ADCs, presented this year again at ISSCC. The challenge now is to migrate these designs to 45 nm CMOS processes.
For the ADC part, the researchers have reported further improvements in performance of a 9-bit 40 Msample/s fully dynamic noise-tolerant successive approximation (SAR) ADC that boasts a figure of merit of 54 fJ/conversion step. The new design is optimized with an improved sample-and-hold and a noise-robust approach by leveraging redundancy in the search algorithm. It was fabricated in 90 nm digital CMOS and occupies less than 220 × 410 µm
“The ability to develop an innovative RF architecture with scaled-down CMOS technology and circuit technologies in transceiver products supporting next-generation cellular standards such as 3GPP-LTE and 4G's is one of the key differentiators for our products that are superior in cost advantages, performance and power,” said Masao Nakaya, board director and executive general manager of LSI product technology unit at Renesas Technology.
While IMEC is concentrating on the reconfigurability of the front-end architecture, the SDR Forum is focusing on the development and standardization of an application programming interface (API) that would provide a layer of hardware abstraction from the underlying RF front-end/baseband.
To demonstrate a fully operational SDR radio, IMEC is hoping to combine its FLAI platform with the flexible radio front-end by the year-end. This platform achievement will be followed by a new generation of work on SDR and cognitive radio, stated IMEC.
With rapid advances in the performance of CMOS at RF and microwave frequencies, especially at the scaled down geometries of 45 nm, the prospect of combining the RF front-end and baseband functionalities on a single CMOS chip are far greater today. Consequently, it can help deliver a true low-cost, low-power SDR solution to mobile handsets that can single handedly roam around the world without any hindrance, as well as offer myriad other features like WiFi, Bluetooth and WiMAX.
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