Converter bandwidth is largely determined by the size of the sample capacitors used in the ADC. Bandwidth is inversely proportional to the value of the sample capacitor as shown in equation 1. This is easily observed by considering that the sample process consists of a finite resistance sample switch and a sample capacitance. In this case, it is readily apparent that bandwidth is determined by the combination of the switch resistance (and any external series resistance) and the sample capacitor. Therefore, to maximize input bandwidth, both R and C should be minimized (Figure 1).

Wider input bandwidth allows for better slew rate performance and more accurate tracking of fast-slewing analog signals associated with both transient events and high-frequency sine waves. It also allows wideband analog signals to be accurately sampled and is often accompanied by a faster sample rate.

Conversely, wider input bandwidth allows more noise to pass the ADC input stages and be digitized, resulting in lower SNR than would have for a lower-bandwidth ADC. This is the reason many high-bandwidth ADCs have lower SNR performance than otherwise predicted. If the sampling rate is high enough the input noise will be widely distributed across the Nyquist band and digital filtering can remove excess noise should the desired bandwidth fall within a Nyquist band of the ADC. However, if the sample rate is much less than the analog input center frequency the input noise will be aliased into the Nyquist zone and the noise density can become quite high. Therefore, great care must be taken both in the design and use of wide bandwidth ADCs.

In reality, wider bandwidths are only necessary for wideband signals such as transient events. High-frequency sampling only needs sufficient bandwidth to sample the signals of interest. Since most common signals are bandlimited both for performance and regulatory reasons, ‘wider’ bandwidth is not a necessary requirement of IF undersampling. Because of this, a class of ADCs called bandpass converters allow high-frequency signals to be digitized without the excess bandwidths. This results in low-distortion sampling and high SNR performance in the signal band of interest. These are typically found as bandpass delta-sigma converters and are often used in highly integrated receiver functions such as those used in Wi-Fi chipsets. Other examples for more general-purpose usage can be seen in products like the AD6600 (Figure 2). Its noise improvements are achieved by allowing the internal analog network to be resonated at the desired IF to improve unit SNR and to provide rejection to signals outside the band of interest. Standard converters may also be resonated for improved performance, reducing the drive requirements, improving noise performance and filtering input spurious^[5].

The IF undersampling technique has long been sought as a means for reducing the complexity of a receiver design. In fact, sampling as close to the antenna as possible offers the possibility of reducing the size and complexity of the receiver function in a system. Most modern cellular base stations implement IF sampling allowing one or more IF stages to be eliminated from their system reducing both cost and complexity.

While IF undersampling does reduce overall system cost, there is a performance trade off in that IF undersampling ADCs in the past have generally resulted in lower performance than baseband sampling ADCs. Over the past few years, this requirement has driven the demand for high-performance IF sampling ADCs and are now available that are optimized for SNR and SFDR for frequencies as high as 450 MHz.

Sample rates are driven by several factors. The largest driver is to have a sample rate that is an integer multiple of common data rates for communication standards. For example, CDMA2000 has a base symbol rate of 1.2288 MHz, WCDMA has a base rate of 3.84 MHz and TD-SCDMA has a base rate of 1.28 MHz. Based on these rates, common sample rates of 78.6, 92.16, 122.88 and 245.76 megasamples per second (Msps) are common. As in the past, the ADC technology determines the preferred sample rate. And over the past few years, the preference is to run above 80 Msps in most new designs.

Higher sample rates do improve noise performance of ADCs. While the overall integrated noise does not improve, the distribution of the noise over wider bandwidths does offer improvements in noise spectral density (NSD). The lower the noise spectral density, the more sensitive a receiver can be designed. This process is often referred to as processing gain and is nothing more than distributing the same noise over a wider band of frequencies and then digitally filtering out the noise in the frequency bands that are not of interest. Doubling the sample rate can improve the noise spectral density by a factor of 3 dB resulting in a significant improvement in performance of many systems.

However, there are limits to how much sample rates can be increased. Current FPGA^[1] and ASIC^[1] technology limits CMOS^[1] data rates to about 250 MHz, LVDS^[1] to approximately 800 MHz and PECL^[1] to approximately 1.5 GHz. Other logic schemes such as CML^[1] offer the possibility of even higher rates. While some applications have moved to LVDS and PECL, the bulk of applications are implemented in CMOS. This will change in the future, but for now, the mainstream driving applications are still CMOS.