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Synopsys, Inc. has introduced its DesignWare USB 2.0 nanoPHY. This is the first 45-nm USB 2.0 PHY IP to comply with the USB Implementer's Forum Hi-Speed USB PHY certification. This mixed-signal IP uses half the power and die area of previous USB PHY IP solutions and enables faster time-to-market with reduced risk.

The IP is well suited for high-volume applications where the key requirements include minimal area and low power consumption. In addition, the DesignWare USB 2.0 nanoPHY IP has unique built-in tuning circuits that enable quick, post-silicon adjustments to account for unexpected chip/board parasitics or process variations without the need to modify an existing design. This feature enables designers to increase yield and minimize the cost of expensive silicon re-spins.

The DesignWare USB 2.0 nanoPHY is part of the complete USB 2.0 IP solution from Synopsys that includes the USB 2.0 digital controllers, PHY and verification IP. Synopsys offers a comprehensive portfolio of USB IP for 180-nm, 130-nm, 90-nm, 65-nm — and now 45-nm process technologies.

The logo-certified DesignWare USB 2.0 nanoPHY IP for the 45-nm process is available now. In addition, the USB 2.0 nanoPHY for the 40-nm process is currently scheduled to become available in the second half of 2008.

The complete DesignWare USB 2.0 solution, including the PHY IP (ranging from 180-nm to 45-nm), digital controllers and verification IP is available now.