Bringing SOI to fabless IC design houses
Silicon-on-insulator (SOI) IP developer SOISIC has announced that one of its leading foundry customers has successfully produced six working ICs using an ASIC-based SOI design process. As a result, fabless IC companies can realize the significant performance advantages associated with SOI by using the manufacturing services of a top-tier Asian foundry.
Previously, the only semiconductor companies able to produce leading-edge SOI devices were integrated device manufacturers (IDMs) with their own multibillion-dollar fabs and fully custom design methodologies. Now, for the first time, SOISIC and its foundry customers are making SOI technology available to the fabless ASIC design community by providing breakthrough IP with design libraries developed to solve SOI design complexities. Since SOISIC's IP fits seamlessly into customers' existing design flows, designers can quickly and cost-effectively create SOI-based chips that deliver the performance and power advantages needed to continue Moore's law.
According to Eduard R. Weichselbaumer, president and CEO of SOISIC, SOI is well on its way toward mainstream adoption by the global semiconductor industry, as next-generation challenges create a growing need for SOI-based device designs. “Leading IDMs have demonstrated the performance advantages associated with this innovative technology. Many leading-edge PCs, servers and gaming systems are powered by SOI-based microprocessors. Now with the successful production of SOI-based devices at a top foundry, the stage is set for broader SOI adoption by the fabless design community.”
The major foundries have announced, or are expected to declare, the future availability of SOI manufacturing processes at the 90 nm or 65 nm design nodes. Such widespread foundry adoption will facilitate SOI proliferation in the ASIC and customer-owned tooling (COT) markets, where several factors are expected to drive adoption.
The first is the demonstrated advantages of SOI, which can boost device performance by as much as 30% and deliver power efficiency gains of up to 50% over bulk CMOS designs. The second factor is the widespread availability of SOI COT design kits and IP that will enable fabless companies to seamlessly integrate SOI into their existing design flows. Finally, there are economic arguments that make this technology compelling. In fact, the cost of a finished die on SOI is expected to be competitive or even lower than bulk CMOS processes for many applications at advanced nodes, according to SOISIC. Equally attractive are the potential system-level cost savings due to the power/performance advantages inherent in SOI-based chips, added SOISIC.
Proving the production worthiness of SOI in a foundry model, SOISIC, on its first pass, successfully taped-out and validated standard cells with three Vts, input-output circuitry and memories, as well as a data encryption and decryption circuit, consisting of eight million transistors. These tape-outs of devices based on SOISIC's IP libraries also validate the company's COT design kit. Developed to seamlessly fit into industry-standard EDA tool flows, SOISIC's design kit does not require specific tools or engineer retraining, since all SOI-specific effects are transparently handled at the IP level. SOISIC continues to work with major EDA tool vendors to enhance their tool capabilities, and the company's full design kit is available to designers.
For more information, visit www.soisic.com
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