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Attenuators perform the important function of amplitude control in a high-frequency system. Microwave RF attenuators are available in many package styles and formats, including fixed-value attenuators (which are also referred to as pads), continuously variable attenuators and digitally programmable attenuators. Continuously variable attenuators, for example, are useful for emulating the propagation and multipath losses of signals between transmitters and receivers in a wireless link. Programmable attenuators are widely used in test equipment, such as signal generators, to control the output levels of test signals. Fixed attenuators are useful for improving the impedance match between components in a system, such as a filter and an amplifier, when the attenuation loss can be tolerated.

Digital attenuators have a distinguishing feature in that a known amount of attenuation can be selected at high speed according to the state of a logic signal. Digital attenuators are available commercially with and without driver circuitry. The type of logic used with the attenuator depends on the driver, with transistor-transistor logic (TTL) and most CMOS logic levels being available. When there are many bits, the external driver becomes complex. In such cases, the circuit designer needs to spend a significant amount of time in implementing the driver. A multibit driver also increases component count, reduces reliability and occupies board space. In attenuators built using gallium arsenide (GaAs) MESFET or PIN diodes, some makers incorporate the driver as a separate die inside the package at the expense of package size and increased cost. However, in the case of super RF CMOS attenuators, the driver is integrated on the same die, reducing the package size, cost and complexity.

Unlike continuously variable attenuators, digital attenuators switch in discrete, finite attenuation states, usually in binary steps. By using semiconductor devices such as GaAs MESFETs, PIN diodes or MOSFETs to achieve different attenuation states, switching can be performed at speeds comparable to solid-state switches.

Bits and attenuation

Digital attenuators are specified in terms of the number of bits of attenuation, such as a five-bit attenuator or a six-bit attenuator. The bits do not command equal amounts of attenuation but select increasing amounts of attenuation. The least-significant bit (LSB) selects the smallest amount of attenuation offered by the component, while the most-significant bit (MSB) selects the largest amount of attenuation, with attenuation values in-between selected by the remaining bits. When all bits are selected, a digital attenuator provides its maximum rated attenuation. When only the LSB is selected, it provides its minimum attenuation step. Temperature variation of attenuation and accuracy dictate the LSB value that can be achieved, given a requirement of monotonic variation. The lower the temperature variation and the higher the accuracy, the smaller the minimum attenuation step. In critical applications such as cellular code-division-multiple-access (CDMA) base-station transceivers, which rely on precise amplitude control, a minimum attenuation step of 0.5 dB may be required.

MSB attenuation value is dictated by the variation with temperature and frequency and the isolation of the internal switches. It is also decided by the semiconductor process variation. For instance, super RF CMOS attenuators provide an MSB up to 16 dB, which is comparable or higher than the best available attenuators in the industry.

Most communications systems use 50 Ω impedance except for cable television, where 75 Ω impedance is used. Few manufacturers cater to both impedance requirements. Super RF CMOS attenuators are available in both impedances of 50 Ω and 75 Ω.

A digital attenuator's frequency range should be matched to the application of interest. For example, a component targeted for IEEE 802.11b/g wireless local-area network (WLAN) systems should provide coverage of at least 2400 MHz to 2500 MHz. For cellular base stations, 800 MHz to 1000 MHz range is required. When the frequency range of a component is broad, it can be used in many systems. This reduces the number of different components to be stocked by the user and reduces the design time for new systems by eliminating or reducing the qualification requirement of a new component. It also results in lower cost due to large quantity purchase, which is a result of using the component in several applications. Super RF CMOS attenuators cover a wide frequency range. For 50 Ω systems, some super RF CMOS attenuator models are specified from dc to 4.0 GHz and others have usable performance over that range. These attenuators satisfy a variety of applications in wideband systems such as instrumentation, and narrowband applications including cellular, WIMAX, PCN, UMTS, wireless LAN, UNII, HyperLAN, and defense communications.

For 75 Ω systems, super RF CMOS attenuators cover a frequency range of dc to 2.0 GHz. Applications above 1 GHz in 75 Ω systems are few. Hence, these attenuators satisfy the present and future needs of the CATV industry.

Users of digital attenuators have tended to consider them ideal in their control of signal amplitude. But these are not ideal components and, in addition to the tolerance on their nominal attenuation values, they exhibit insertion loss. One way to think of this is to consider the loss of the component when its attenuation value is set to 0 dB. Most of the insertion loss (attenuation in the 0 dB state) is due to the loss of the internal switches. In a six-bit attenuator, the loss is due to as many as 12 SPDT switches in cascade. Design techniques and semiconductor technology dictate what can be achieved to minimize this effect. Low-loss switches employed in super RF CMOS attenuators provide the best insertion loss in the industry.

Switching speed is another key digital attenuator parameter and is a function of the type of active devices used, typically PIN diodes or GaAs MESFETs or CMOS. Data sheets for digital attenuators are not standardized in their representation of this performance parameter, and it is important when comparing digital attenuators to fairly match-up switching-speed specifications. One of the more common conventions is to measure a digital attenuator's switching speed in the manner of an RF switch: from 50% of the control signal to 90% of a new amplitude level. This approach considers the delays contributed by the logic driver circuitry that is usually operating with TTL or CMOS control signals. In cases where the ultimate driver speed is needed at some expense in current consumption, ECL drivers may also be considered. Super RF CMOS attenuators are specified for 50% control to 0.5 dB from the final attenuation value, which is more meaningful for the user.

RF CMOS attenuators

A digital attenuator is specified in terms of the dc power it consumes and the RF power it handles. Depending on the type of driver and attenuation circuitry, digital attenuators are usually designed for low-voltage (+5 Vdc or less) and current consumption of 20 mA or less, which is generally considered low. Many battery-powered applications require the lowest possible current. CMOS circuitry used in super RF CMOS attenuators requires negligible current (100 µA), which helps to conserve battery power.

Digital attenuators are also rated for acceptable RF input power, usually in terms of the 1 dB compression point and occasionally in terms of the maximum acceptable input power level that can be tolerated without damage to the attenuator. Of course, exceeding a digital attenuator's 1 dB compression point generally results in the generation of elevated output harmonic and spurious signal levels due to the non-linear behavior of diodes or FETs used in digital attenuators. Due to high linearity of FETs used in super RF CMOS, the attenuator is specified for 0.2 dB compression instead of 1 dB. Because of the linearity requirements of modern applications, digital attenuators are now often characterized in terms of their input third-order intercept point (input IP3), with higher values denoting better linearity performance. The linearity of FETs used in a super RF CMOS attenuator provides the best performance over the entire band starting from 1 MHz. Digital attenuators built with MESFETs lose performance below a few hundred megahertz.

An important parameter in characterizing digital attenuators is the voltage standing wave ratio (VSWR), which is often shown as return loss. It is essentially a measure of how well the component will transfer energy with minimal reflections and power loss from and to other components in a system. When considering a wideband component for narrowband use or for multiple-frequency-band operation, it should be noted that VSWR varies as a function of frequency. Optimum performance can usually be found at midband frequencies. Some of the wideband digital attenuators in the industry have a return loss as poor as 11 dB, vs. 20 dB typical for a super RF CMOS attenuator, which now sets the standard.

Digital attenuators are fabricated with a variety of different technologies, including monolithic chips, assemblies on low-temperature co-fired ceramic (LTCC) substrates, and hybrid circuits. In most cases, specifiers will require a certain package style and footprint size for their application, and digital attenuators are available in a variety of package styles, ranging from miniature surface-mount technology (SMT) to machined-aluminum housings with coaxial connectors. Package size and style should be considered as part of a digital attenuator selection process that includes a list of environmental requirements, such as required temperature range, whether hermetic packaging is needed, and other screening requirements.

Mini-Circuits has developed a new series of digital step attenuators (DAT) using super RF CMOS technology with an unprecedented combination of accuracy, linearity, programmability, ESD tolerance, and wide bandwidth in a small 4 mm × 4 mm × 0.9 mm surface-mount package. This attenuator family includes models requiring only a single positive or positive-negative supply voltage. The supply voltage choice depends on switching speed and ultra low-noise requirements. All super RF CMOS attenuators are configured as a chain of fixed attenuators with bypass switches and an internal driver for control of the switches (Figure 1). While the super RF CMOS attenuator is basically a surface-mount component, the company has also readied connectorized versions for ease of connection and use in the lab, prototyping or in the end systems.

DAT performance

Accuracy: A most important parameter in step attenuators is accuracy, for which super RF CMOS attenuators define the state of art. They are monotonic over the attenuation range, making them easier to program. Figure 2 graphs attenuation vs. frequency and temperature for the 0.5 dB step, showing an accuracy of 0.05 dB typical from dc to 2.4 GHz.

Note the accuracy change with temperature is within ±0.02 dB. As the step size increases, the accuracy changes but not proportionately. Figure 3 shows the accuracy for a 16 dB step.

The accuracy is typically 0.1 dB from dc to 1 GHz and 0.15 dB from 1 to 2.5 GHz. Attenuation variation with temperature is ±0.2 dB, which is outstanding for a big step size. Figures 2 and 3 show that the attenuators have usable performance to 4 GHz.

Impedance match: Good return loss is a requirement for accuracy. Otherwise, the impedance interactions of the attenuator and the devices interfacing with it will create an attenuation ripple. With this in mind, these attenuators have been designed for excellent return loss. Figure 4 shows typical input return loss vs. frequency. Note the return loss is typically 18 dB or better up to 2.4 GHz for all attenuation steps.

Dynamic range: System performance is decided by the dynamic range of the individual components. High-end input power level of the dynamic range of DAT attenuators is specified by compression and third-order intercept point.

One of the greatest advantages of a super RF CMOS attenuator is its IP3 and compression, which remains substantially constant from 1 MHz to the highest specified frequency. Compare this to MESFET- or PHEMT-based digital attenuators, in which IP3 and compression is not constant and starts falling off below about 500 MHz as much as 20 dB. Figure 5 shows that at +24 dBm input power the compression is typically 0.1 dB from 1 MHz to 2.4 GHz. Over a temperature range of -45 °C to +85 °C, the variation is negligible.

These attenuators offer an amazing input IP3 of 52 dBm typical from 1 MHz to 2.4 GHz, as shown in Figure 6. This is better than what can be obtained from PIN diode-based attenuators. Again, by comparison, for GaAs-based attenuators, IP3 starts falling below 500 MHz.

Supply voltage: The super RF CMOS family of attenuators uses a patented CMOS technology and can operate with a positive or a positive and negative supply voltage. In super RF CMOS attenuator models with single positive supply voltage, the internal circuitry turns on a patent-pending low-noise internal negative voltage generator, which produces the negative supply voltage. The DAT models working with dual positive-negative supply voltage do not need the internal generator. For these models the switching speed is 1 MHz compared to 25 kHz for single positive supply voltage models. Users should select the supply voltage based on the switching frequency and noise requirements.

For applications where the system voltage is +5 V instead of the +3 V specified for super RF CMOS attenuators, the user needs to use a resistive voltage divider to reduce the voltage from +5 V to +3 V, as shown in Figure 7. For low-noise applications, and for the applications where the supply voltage varies, one may prefer to use a low-noise low drop-out (LDO) voltage regulator such as MAX8878 (preset to 3.3 V), as shown in Figure 8.

Switching control: The DAT family of models have a unique CMOS circuit that allows them to be immune to latch up. Figure 9 shows the schematic of a six-bit attenuator with 0.5 dB step and parallel control.

Programming DATs

Parallel control can be operated in two modes: direct parallel programming and latched parallel programming.

Direct parallel programming is useful for manual control of attenuation using hardwire, switches or jumpers. Here, latch enable is held at high state and attenuation values change as the control signals state changes.

In latched parallel programming, latch enable is held in low state while attenuation controls are being changed. When change is complete, the latch enable state is pulsed from low to high to enable the change of attenuation and back to low to latch the change. Super RF CMOS attenuators have a provision for setting start attenuation during power up. When the attenuator powers up with latch enable set to zero state, the control bits are set to one of four possible values based on the state of the two power-up bits (PUP1 and PUP2). This defines the start-up attenuation.

Figure 10 shows a six-bit model with 0.5 dB step and serial control. Here, attenuation is controlled by three CMOS-compatible signals: data, clock and latch enable (LE). The data and clock inputs allow data to be serially entered into a built-in shift register. The LE input controls the latch.

The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data are entered. The LE input should then be toggled HIGH and brought to LOW, latching the new data. In the serial mode of control, power-up attenuation state is decided by the state of the six power-up control pins.

No dc coupling capacitors

The internal biasing design of the super RF CMOS attenuators makes dc-blocking capacitors at the RF ports unnecessary. Caution is taken that the user's interfaces do not apply dc externally. This gives the benefit of frequency response extending down to low frequency. In contrast, any MESFET- or PHEMT-based step attenuators need dc blocks, and the frequency response cannot go down to low frequencies.

Digital step attenuators use FETs, which are sensitive to ESD. Built-in ESD protective circuits in the DAT series of attenuators raise the immunity level to +500 V per human body model and +100 V per machine model. This makes them capable of being used with only standard ESD precautions.

These attenuators have a switching time of 1 s. It is an industry-standard convention to define switching time as 50% control to 10% to 90% of RF. GaAs attenuators, have a long tail after 90% for rising signals and before 10% for falling signals. Hence the time necessary to reach the final value of attenuation is much higher and is comparable to super RF CMOS attenuators.

Positive voltage models can work with a switching control frequency of ~25 kHz. Increasing the switching control frequency above ~25 kHz will affect the rise/fall time, which will affect how fast the DATs change attenuation values. This phenomenon will appear more drastically above 200 kHz.

Dual-voltage models can work with a switching control frequency up to 1 MHz without degradation in rise/fall time. Above 1 MHz, there will be some degradation as previously explained.

Conclusion

A series of digital step attenuators has been introduced, which defines the state of the art. A unique combination of accuracy, linearity, programmability, ESD tolerance, positive supply voltage and wide bandwidth in a small size makes them unique in the industry. Port impedance of 50 Ω and 75 Ω makes them suitable for wideband and narrowband applications up to 4 GHz. Plus, they are immune to “latch up,” which is a problem with conventional CMOS circuits.

ABOUT THE AUTHOR

Radha Krishna Setty is director of engineering at Mini-Circuits, Brooklyn, N.Y.