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Conventional mounting techniques are expensive when power amplifiers (PAs) or other high-power flanged RF devices are mounted to printed circuit boards (PCBs). In traditional techniques, the devices are usually mounted on a single-layer board. This board is then mounted onto a metal carrier, which acts as a heat sink and a ground reference for the RF signal. This metal carrier must occupy a large area so that good continuity and heat sinking can be obtained.

While this method works well, it requires a lot of board real estate and hardware. There is now an improved method for mounting high-power devices that occupies less area and gives better ground continuity.

Conventional mounting technique

Figure 1 shows two views of the conventional mounting technique. Figure 1(a) shows the side view of the RF device mounted within a cut-out in the PCB. Bolts are used to fix both the device and the PCB to the base metal carrier. To ensure good heat conduction and ground continuity, the base metal carrier is sizeable compared to the RF device itself, than would otherwise be present in a multilayer board. With the desire for smaller, lighter circuits in modern RF equipment, this is a distinct disadvantage.

Figure 1(b) shows the top view of the arrangement. It becomes clear that the RF device is placed within a cut-out in the PCB material (usually RT/Duroid or similar low-loss RF material). The screws are shown indicating the fixing of the upper dielectric to the base metal carrier below. When this process is finalized, the area used is substantial in relation to the size of the device.

The new method presented here reduces the size of the overall circuit by incorporating heat sinking into the PCB. It also overcomes the discontinuity in the RF ground plane.

Layers and dielectrics

Figure 2 shows the construction of a board made using the new technique. Multilayer PCB designs are described in terms of copper plane construction layers. For the example described here, layer 1 is the RF signal layer, layer 2 is the RF signal ground, layer 3 is the ground for the PA device, and layer 4 is another RF signal layer.

Between these layers are the different dielectrics used for the construction of the multilayer PCB. In this example, a RF laminate has been used for good RF performance within circuit elements around the device. Reduced flow dielectric (usually called no-flow pre-preg) is below this. It has a high glass transition temperature to restrict its flowing during the bonding process required for assembly of the PCB. However, it does flow somewhat in processing.

The no-flow pre-preg should be kept as thin as possible to prevent bulging of the pre-preg into the cavity when the multilayer board is finally pressed and bonded together. As a guideline, 100 mm would be the maximum thickness. The height of the RF laminate can be adjusted so that the overall thickness of the first two layers and first two dielectrics is the same as the overall height of the device being placed in the cavity.


Figure 3 shows the exploded diagram view of the dielectrics used in the multilayer PCB described above. First, a cut-out is made for the device in the top RF dielectric and in the no-flow pre-preg. These two dielectrics are then bonded together. Next, this sub-assembly is bonded to the lower RF dielectric. Though the pre-preg is no-flow, during construction some flowing of the dielectric may occur under the heat and pressure required for the bonding process. This will cause some bulging of no-flow pre-preg into the cavity. In some cases, this may not be a concern as the device may fit loosely in the cavity. In most cases, however, an alternative approach can be taken.

No cut-outs are made before the construction of the PCB. Any excess flow (e.g. from the pre-preg) will then be to the outside walls of the PCB, which can be cleaned up without much difficulty. The cavity for the RF device is manufactured by z-plane drilling (mechanically or by laser drill laser drilling is more accurate but the most expensive). Even though z-plane drilling is costly, the cost is justified by being able to go down to any layer. And, it prevents layer-3 copper (or any other layer being drilled down to) from being broken by a mechanical drill bit.

Layer 1 to 4 vias can be drilled and plated next. This process plates the cavity and provides a low-impedance connection between the signal ground and the device ground, which aids the connection due to adjacent vias and the capacitive effect between the ground planes. Additional layers can now be added to the build as required.

Heat extraction

Two possible methods exist to take the heat away from the device:

  1. The device ground layer is used, ideally deposited with more copper.

  2. Through-holes are drilled and plated through the cavity to the bottom of the board, where suitable heat sinking can be attached or mounted. This includes the possibility of mounting the board directly to a metal box, which can act as the heat sink.

In both cases, plated through-holes would be required for the device's mounting bolts.

A solution for thickness

If the no-flow pre-preg presents a significant thickness, then a discontinuity in the RF signal ground can occur for the RF signal track leading into the RF device. The ratio of the width of the track to the dielectric thickness needs to be kept constant. This is done by removing the RF signal ground adjacent to the device, and increasing the RF track width in this area accordingly (as shown in Figure 4). This reduces the discontinuity in the RF ground for the tracking. Figure 4 also shows a step in the width, which in itself may cause unwanted effects (e.g. reflection). Figure 5 shows the completed assembly, which solves the ground discontinuity problem.

Figures 6 through 9 are a series of diagrams showing the layer-by-layer plan views of each part of the new method's construction of a multilayer PCB.

Figure 6 shows layer 1 with the device clearly visible and the tracking to the device shown. The track has been widened near the pins of the device to overcome the ground discontinuity effect discussed in section 5.

Figure 7 shows layer 2, the RF signal ground, in which the via holes can be seen clearly and the cut-out for the cavity can be seen.

Figure 8 shows layer 3, the device's ground layer. Once again, the via holes can be seen clearly and the bolt holes for the mounting of the RF device. The via holes are placed in several locations around the device for good connection between the RF signal ground and the device ground.

Figure 9 shows the final layer of the construction - layer 4 - which is another RF signal layer. The via holes passing through this layer are, of course, isolated from any signal tracking on this layer to prevent shorting of the tracking (note that figures 8 and 9 appear identical. However, there are slight differences in the model).


A new technique for mounting high-power flanged RF devices has been presented. The technique improves on the conventional method for mounting these devices by making use of a multilayer construction of PCB. This improves ground continuity, reduces the area of board used and gives integrated heat sinking. In addition, possible difficulties with regard to discontinuity of the grounding near the component's pins have been overcome by the use of a larger track width. The use of accurate mechanical drilling, or preferably z-plane laser drilling, has been recommended to prevent damage occurring to layers during the construction process.

About the authors

Kedaar Kale is a senior engineer in Wireless R&D Group, Central Research Laboratories, Hayes, Middlesex, UK. He holds MEng and DPhil degrees, both from the University of Oxford. He joined Central Research Laboratories two years ago and was previously employed by Racal Research in Reading, UK. He can be contacted at +44 (0)20 8848 9779. E-mail: kkale@crl.co.uk .

Adam Loveridge is a principal engineer in Wireless R&D Group, Central Research Laboratories, Hayes, Middlesex. He holds a BEng degree from Salford University. He joined Central Research Laboratories three years ago and was previously employed by Ericsson, Nokia and GEC. He can be contacted at +44 (0)20 8848 9779. E-mail: aloveridge@crl.co.uk .

The authors wish to thank Central Research Laboratories' PCB manufacturers for useful discussions regarding the technical capabilities of modern PCB houses. and Central Research Laboratories' Wireless R&D Group for their support in completing this work and article.