Spurious levels on the output of a phase-locked loop (PLL) that generates a carrier signal are an important specification in many RF systems. Spurs may come from a variety of sources, but one of the most common is the PLL's reference clock. This spur is often referred to as the reference spur, or reference feedthrough. The existence of this spur is not surprising because many of the PLL's components including the phase-frequency detector (PFD) and charge pump (CP) are clocked at the reference frequency (fref). Spurs from these sources can be seen in the PLL's output spectrum, offset from the PLL's output frequency (fout) by ±fref as shown in Figure 1. The spurs are caused by non-idealities in the PLL components such as mismatched propagation delay in the PFD and CP, charge injection and current mismatches in the CP, and leakage current on the VCO tuning node (VCONTROL).

Running a transient simulation, waiting for the loop to settle, and measuring the spectrum of fout can simulate a PLL's reference spurs. Simulation by this method can be time consuming and inefficient, especially if the feedback ratio (M) of the PLL is large. This is because the simulator needs to calculate its time step small enough to accurately capture fout. If M is large, the time step will be small compared to the settling time constant of the PLL, resulting in a long simulation run time to lock the PLL. In addition, a larger M results in more fout cycles that are needed to capture the fout spectrum including the reference spurs.

If the PLL components have sufficient power supply rejection, we can assume the reference spurs on fout are dominated by direct modulation of the VCO input. This allows us to replace some of the components of the PLL with behavioral models to decrease simulation run time. Two improved methods to evaluating PLL reference spurs caused by direct modulation of VCONTROL are shown in Figure 2. Both methods use behavioral models to eliminate the high-frequency edges of fout. This requires the simulator to calculate fewer time steps, resulting in a reduction in transient simulation run time. Another advantage of the improved simulation approaches is that the circuitry reduction makes the PLL easier to simulate in a periodic steady-state (PSS) simulator such as SpectreRF. Use of a PSS simulator further reduces the simulation run time, and makes accurate determination of the spectrum trivial.

Using the DLL approach, the fout signal is not directly available and another method needs to be used to determine the fout spectrum. If we assume that the modulation of VCONTROL results in only a small phase error on the VCO output (narrowband FM), we can use the spectrum of VCONTROL to calculate the spectrum of fout.

Spur in dBc = 20 · log10

where vn = peak voltage measured at ƒn in the spectrum of VCONTROL. This equation can be tested by simulation of an open loop behavioral VCO with two 1 mV peak sine waves with frequencies f1=100.586 MHz and f2 = 200.195 MHz added to VCONTROL. The VCO gain is KVCO = 200 MHz/V, and the VCO center frequency fVCO = 2.0 GHz. Using equation 1 with vn = 1 mV, and fn = f1 or fn = f2 yields spur levels that match the simulation results shown in Figure 3.

In the future, when increased computing power is available, simulating any architecture PLL to evaluate reference spurs may be trivial. With present computing limitations, the improved simulation approaches described here reduce the number of transient simulator time steps required to evaluate a PLL's reference spur levels. This simplification results in a reduction in simulation run time. A further reduction in simulation time can be achieved by using a PSS simulator, and a basic calculation to evaluate PLL output spectrum based on the VCO control voltage spectrum.


Steve Williams is a principal analog/RF IC design engineer and Tony Caviglia is an analog/RF IC architect. Both are with Cadence Design Systems' Cadence Design Services in Columbia, MD.

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