In today's wireless handset market, extending battery life for increased standby and talk time continues to be a paramount goal. Because battery technology isn't yet up to the task, accomplishing this goal requires an effective means to manage power consumption while maintaining a high level of RF performance. This is especially true in the case of the handset power amplifier because it consumes the greatest amount of battery power.

The design of the power amplifier for CDMA mobile phones is usually constrained by linearity requirements at the maximum power output, regardless of the average power transmitted by the radio. As a result, the quiescent bias of the amplifier is set for maximum linear power and DC power is wasted at lower levels of output power. To overcome this condition, power can be managed more efficiently by employing a flexible or adaptive DC bias approach to significantly reduce average operating current.

In most IS-95 CDMA applications (depending on geographic factors), the typical power transmitted by just the radio requires the power amplifier to operate at a 10 to 20 dB back-off from its maximum rated linear power. Infrequent operation at maximum power requires a higher quiescent DC current for the amplifier, but backed-off operation can be achieved using far less quiescent and operating current while maintaining high signal linearity. For this demand, heterojunction bipolar transistor (HBT) power amplifiers step up to the plate. Such devices allow operating current to be minimized relative to the output power requirements of the handset. This eases the demand on power.

Power amplifier attributes

A simplified block diagram of a PCS (1.850 to 1910 MHz) power amplifier module is shown in Figure 1. The two-stage MMIC amplifier is manufactured using an InGaP HBT process, and the module is internally matched to 50Ω at the input and output ports, significantly reducing the end product's external part-count. Molded encapsulated packaging provides a compact and low-profile LCC outline of 6 × 6 × 1.5 mm³ that reduces the handset board space requirements. Typical performance for the amplifier under IS-95 CDMA modulation includes 26 dB gain, 33% efficiency and -50 dBc ACPR at an output of +28 dBm.

This particular amplifier module is designed for cellular, PCS and W-CDMA mobile phone applications. Such amplifiers can adaptively control DC power consumption by varying the reference voltage input (V_ref) only. Further, DC power management can be implemented in either analog (continuously variable) or digital (stepped voltage) modes, giving the handset designer a variety of options to save operating current under low levels of RF output power and to extend the battery life in next-generation mobile phones.

DC bias circuit design

As illustrated in Figure 2, the on-chip DC bias network consists of a simple form of current mirror where the total emitter area of the mirror device is scaled relative to the RF amplifying transistor. Based on a nominal reference voltage of +2.7 VDC, the value of reference resistor, R_ref, is then calculated from the V_be turn-on voltage of the HBT (typically 1.27 VDC), the mirror-to-RF device area ratio and the quiescent collector current (I_ccq) required to meet linearity requirements at maximum rated power (+28 dBm). For IS-95 CDMA applications, a mirror-to-RF device size ratio of 1:6 was chosen to ensure that the current source delivers adequate base current to the active device under peak RF drive conditions. A choke inductor or resistor for low-current gain stages is required to isolate the DC bias network from the RF circuitry.

While GaAs HBT technology allows positive-only voltage operation to simplify handset design, the high base-emitter diode voltage of the transistor places a significant constraint on bias circuit design when operating from low battery voltages (3 VDC or less). For example, an alternative current-source design with current gain replaces the collector-base connection in the mirror circuit with a base current driver¹. The net result is that there are now two base-emitter diode drops (~2.54 VDC) between the reference voltage input and ground. This fact, combined with the temperature sensitivity of the base-emitter diode voltage (-2 mV/° C) would limit the effectiveness of the current source at cold temperatures (-30°C) and prevent its use for adjustable bias control. Conversely, the simple current mirror design incurs only a single V_be diode drop from the reference pin to ground, which makes it suitable for use at low reference voltage (e.g. 1.7 VDC) and adaptive DC bias control.

Typically, this device requires a reference voltage of +2.7 VDC for fixed-bias applications. However, V_ref can be increased to add quiescent current for higher linearity. Preferably, reference voltage will be decreased to reduce idle current and PA operating current at lower levels of transmitted power. Nominally, reference voltage can be adjusted over a range of 1.7 to 3.2 VDC, providing a great opportunity to optimize the DC bias conditions of the amplifier. As shown in Figure 3, quiescent current (I_ccq + I_ref) linearly decreases with decreasing reference voltage, reducing idle current to less than 30 mA at V_ref = +1.7 V. The net result is a 60% savings in idle current compared to fixed-bias operation. A tremendous improvement in standby time for the handset results as well.

Adaptive DC bias control

Some power amplifiers are capable of adaptive DC bias control using either analog or discrete modulation of the reference voltage. However, to illustrate the effectiveness of DC power management, application and measured results will focus primarily on digital-mode bias control techniques.

Figure 4 shows a typical block diagram for a mobile phone transmitter and one possible implementation of digital bias control. As illustrated, available signals from the baseband processor are used to control an external complementary metal-oxide semiconductor (CMOS) switch and an adjustable, low-drop-out (LDO) voltage regulator that sets the reference voltage for the power amplifier. The enable/shutdown feature of the regulator provides a low-leakage (2 μmA typical), hard power shutdown for the HBT amplifier by forcing the V_ref pin to 0 VDC. When the power amplifier is active, separate controls are used to set the PA reference voltage to 2.7, 2.0 or 1.7 VDC, representing high (>+16 dBm), mid and low (<+4 dBm) output power ranges, respectively, for the amplifier. Table 1 summarizes the operating conditions and typical performance of the PA when operated using digital DC power management.

Linearity-DC power trade-off

A critical requirement for reducing DC power consumption in CDMA power amplifiers is the need to simultaneously meet IS-95 requirements for adjacent channel power ratio (ACPR) or linearity. Because linearity is closely related to the saturated power capability of the amplifier, a practical trade-off exists between DC power reduction and ACPR. This is especially important at RF power levels well backed-off from maximum rated linear power because these operating conditions provide the best opportunity to save DC power and extend handset battery life.

Typically, to satisfy the linearity requirement, DC bias conditions must be sufficient to give the PA a saturated power capability that is 3 to 4 dB higher than the RF output power at which linearity is measured. For example, an ACPR of -50 dBc at +28 dBm requires a PA saturated power of about +31 dBm to +32 dBm for quiescent bias conditions at a reference voltage of +2.7 VDC. Of course, these results assume that the amplifier has been designed with appropriately sized active devices and a compromise output load match for high linearity and good efficiency.

Nominally, for fixed-reference voltage operation at +2.7 VDC, adjacent channel power ratio (ACPR) will continue to improve as RF output power is gradually backed off from maximum rated linear power (+28 dBm). A graphical representation of the linearity-DC power trade-off for both fixed-bias operation and digital DC bias control is shown in Figure 5. Normally, for fixed reference voltage operation at +2.7 VDC ACPR will continue to improve as RF power output is gradually backed-off from the maximum rated linear power (+28 dBm). However, in this mode of operation, excess linearity margin is attained at the great expense of high DC power consumption. These modern PA modules employing adjustable bias techniques allow the system designer to set an acceptable threshold of linearity at minimum DC power consumption while still exceeding the FCC handset requirement for ACPR of -42 dBc.

Real-world operating conditions

Using the operating conditions for digital bias control as defined in Table 1, low-, mid- and high-power ranges of PA output power have been defined with the intent of maintaining a minimum ACPR at + 1.25 MHz offset of -48 dBc. Within each of these operating ranges, the selected V_ref voltage is applied to the PA module to minimize DC power consumption while providing sufficient saturated power capability in the PA to ensure linear operation. At RF output power levels less than +4 dBm, a V_ref of 1.7 VDC provides more than 50% reduction in operating current, on average, while allowing ACPR to gracefully degrade with increasing RF output power. Whenever radio transmission requires more than +4 dBm, power-sensing within the handset (in conjunction with baseband electronics) switches the PA reference voltage to the next higher setting of 2.0 VDC. This incrementally increases the bias current available to the monolithic microwave integrated circuit (MMIC) amplifier. The most notable effect is an immediate improvement in ACPR of about 6 dB.

Linearity performance in the mid-power range follows a trend similar to that of the low-power mode; ACPR again gradually degrades with increasing RF output power until reaching the high end of the user-defined range (+16 dBm). At PA power levels greater than +16 dBm, a final adjustment is made to increase the reference voltage to 2.7 VDC, making the highest level of DC bias current available to the amplifier and resulting in a typical ACPR of -50 dBc at +28 dBm output power. A comparison of ACPR performance at +16 dBm for V_ref levels of 2.0 and 2.7 VDC shows a dramatic improvement of more than 10 dB in amplifier linearity in switching to higher bias voltage. Although it may appear that a large penalty was paid in reducing reference voltage from 2.7 to 2.0 VDC, the system designer still meets the requirement for good linearity while enjoying the reward of a 30% reduction, on average, in DC power consumption at mid-range power levels.

It's not cast in stone, however

Even though the plotted results using digital-mode bias control suggest hard limits for RF output power ranges, these levels are truly user-defined and can be uniquely tailored by the handset designer to fit the requirements of a particular radio or power density profile of a wireless network region. For example, if high linearity is important and average transmitted power is low (e.g. 0 dBm to +8 dBm), the system designer could define mid-power range with endpoints at -4 dBm and +8 dBm to maintain an ACPR of less than -52 dBc in full current-saving mode. There is also no limit to the number of defined output power ranges or reference voltage changes that can be used, other than the usual realities wrestled with in complexity vs. cost.

Current reduction at RF back-off

Now that linearity requirements have been satisfied using reference bias control to minimize DC power, the direct savings in operating current can be examined. Operating collector current under fixed-bias and digital-mode bias control is directly compared in Figure 6. As before, the low-power range is defined as any transmitted power level to +4 dBm while the mid-power range is specified for operating powers between +4 dBm and +16 dBm. Relative to current consumption at 2.7 VDC reference, a 20% reduction in operating current can be realized at an output power of +16 dBm when the reference voltage is lowered to 2.0 VDC. The savings in power consumption is even more substantial at +4 dBm output, resulting in 48% lower current when the PA module is biased at a minimum reference voltage of 1.7 VDC. At all back-off power conditions, IS-95-compliant linearity is maintained.

Assuming that average transmitted power at the antenna is +12 dBm and isolator, duplexer and antenna losses following the PA module are about 4 dB, the saving in DC power consumption at a PA output power of +16 dBm should correlate with the expected improvement in handset talk time. Thus, if PA operating current can be reduced 20% by varying the reference bias voltage, average battery life in a CDMA handset can be extended by as much as 25%.

Gain control in current-saving mode

Naturally, as DC quiescent bias and operating current are reduced through reference voltage control, amplifier gain will also be reduced and must be considered in determining overall transmitter behavior. Depending on the particular method used for DC power management, the gain of the PA module can be continuously varied (analog mode) or digitally changed using a stepped reference voltage. In either case, gain control characteristics of the power amplifier can be combined with those of the handset AGC and driver amplifier to define the overall dynamic range of the radio transmitter.

Under analog control, a 10 dB change in small-signal gain (P_out = 0 dBm) can typically be achieved by reducing the reference voltage from 2.7 to 1.7 VDC. Similarly, digital-mode gain control is illustrated in Figure 7 for the output power ranges previously described for low-, mid- and high-power operation. At a fixed reference voltage of 2.7 VDC, PA gain enhances by less than 3 dB over a wide range of linear output power. This results in a nominal gain of 27 dB at +28 dBm output power. Nominal gain at V_ref = 2.0 VDC is 20 dB, dropping to a typical gain of 12.5 dB at minimum V_ref = 1.7 VDC. Thus, by stepping the reference voltage down to 2.0 VDC for the mid-power range and again to 1.7 VDC for output power less than +4 dBm, linear gain for the amplifier can be controlled over a dynamic range of more than 14 dB.

Conclusion

Adaptive DC power management provides system designers with an effective tool to reduce power consumption in handset power amplifiers and extend battery life in mobile phones. Digital and analog methods of bias control, by reducing operating currents, can potentially increase mobile phone talk-time by 25% or more while still meeting IS-95 CDMA linearity requirements. These same techniques lower power amplifier idle current by as much as 60%, providing the opportunity to improve standby performance of the phone.

About the authors

James A. Roche is the director of CDMA product development at Raytheon RF components. He has more than 17 years experience in design and development of GaAs MMIC devices, processes and products. He has managed MMIC product development at Raytheon, with responsibility for design of MESFET, pHEMT, mHEMT and HBT-based MMICs for commercial and military applications from 800 MHz to 77 GHz. He is also responsible for the development of InGaP HBT power amplifier modules for AMPS/CDMA and W-CDMA mobile phones. He received his BSEE degree from Rensselaer Polytechnic Institute in 1980. Roche can be reached at james_a_roche@rrfc.raytheon.com.

Richard M. Healy is a principal engineer at Raytheon RF Components responsible for the design of InGaP/GaAs HBT power amplifier modules for PCS and W-CDMA handset applications. He has been engaged in the design and development of GaAs FET, PHEMT HBTs, MMICs, hybrid amplifiers and other circuit components since 1976. He received B.S. and M.Eng. degrees in electrical engineering from Cornell University in 1970 and 1971, respectively.

Sara A. Caron joined Raytheon in 2000 as a senior design engineer and has been responsible for design and test of CDMA PA modules for wireless communications. She has more than 15 years experience in developing RF modules for defense and commercial applications. She received her BSEE degree from University of Lowell in 1982 and is currently completing degree requirements for an MBA at Southern New Hampshire University.

Gary Hau received his Ph.D. degree from the University of Leeds, U.K., in 1998. He is currently a senior design engineer at Raytheon RF components where he is involved in the development of CDMA power amplifier modules for mobile handsets and LNAs for wireless LAN applications. Hau can be reached via email at gary_hau@rrfc.raytheon.com.