The performance of analog PLLs has steadily improved, with operating frequencies extending up to 8 GHz and beyond. Industry mainstays for many years, these PLLs are well understood, and offer inexpensive solutions for frequency synthesis and jitter clean up. Recently, digital PLLs based on direct digital synthesis (DDS), have emerged as attractive alternatives in certain applications. This article explores the differences between analog PLLs and DDS-based digital PLLs, and how these differences can be used to guide the designer toward the best option.

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A digital PLL implements traditional PLL building blocks using digital logic. While there are many ways to implement a digital PLL, this article will focus on DDS-based digital PLL architectures.

Figure 1 shows a typical analog PLL. The reference divider, which is the first block encountered by an incoming signal, is no different from that of an analog PLL. The reference divider reduces the frequency of the incoming signal before it goes to the phase detector. The reference divider setting plays a key role in PLL behavior. If the designer must use a large reference divider and a low phase-detector frequency to generate the desired output, the maximum loop bandwidth will be constrained.

The digital phase detector

In an analog PLL, the phase detector generates charge-pump current pulses, whose duration is proportional to the phase difference between the reference and feedback signal. In a digital PLL, on the other hand, the phase detector's output is a digital number proportional to the time difference between the edges of the incoming reference signal and the feedback signal. These digital words are sent to the digital loop filter, which filters and integrates the phase detector output. Because the loop filter parameters are numerical coefficients, however, they can be easily changed, and unlike an analog PLL, there is no practical limit to how large they can be. In addition, the digital phase detector doesn't suffer from thermal noise, aging or drift, and charge pump mismatch or leakage. Charge pump leakage occurs when the transistors in the charge pump do not completely turn off, or another leakage path causes unwanted voltage variation at the VCO. The last advantage is particularly important as charge-pump leakage and driver up/down current mismatch are key contributors to spurs that appear in the output spectrum at the phase detector frequency. The digital PLL avoids this by eliminating the charge pumps.

The digital VCO: DDS plus DAC

In a DDS-based digital PLL, such as the one shown in Figure 2, the DDS block and DAC replace the traditional VCO. The DDS input is a digital-tuning word whose value is proportional to its output frequency. This is similar to a conventional VCO, in which the output frequency is usually proportional to analog input tuning voltage. A typical DDS that runs at 1 GHz will have a fundamental tuning range from dc to about 400 MHz. This range can be extended by using a DAC image above the Nyquist frequency (one-half of the DAC sample rate). The DAC output is sent to an external low-pass reconstruction filter to remove undesired harmonic content, and then back to the on-chip feedback divider, thus closing the feedback loop.

The external DAC reconstruction filter is one important component not found on an analog PLL. This low-pass filter removes frequency content above the fundamental output frequency, leaving only the desired sine wave. A fifth- or seventh-order low-pass filter is common, depending on the filtering requirement and how close the output fre-quency is to the Nyquist frequency. This sine wave can then be fed into a fan-out buffer to produce a square wave clock output. A band-pass filter can be used instead of a low-pass filter for additional noise filtering, or to allow the PLL to operate at frequencies well above the Nyquist frequency. It is possible to get an unfiltered spur at or below the output frequency, so the designer must be careful to do frequency planning and run the DAC at a frequency where this is not an issue.