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Once the component blocks used in a digital PLL are understood, the benefits associated with these digital elements become apparent. For example, the digital PLL excels in frequency translation applications, such as translating the common 19.44 MHz networking clock frequency to 156.25 MHz. This necessitates dividing the incoming signal by 1944, and running the phase detector at 10 kHz. In order to maintain loop stability, the maximum PLL loop bandwidth is typically constrained to about 10% of the phase detector frequency (or 1 kHz in this case). Fractional-N analog PLLs can enhance loop flexibility by keeping the phase-detector frequency high, but this architecture can introduce its own set of problems.

Furthermore, in an analog PLL, low loop bandwidths require bulky loop-filter components, which not only take up board space, but lead to self-resonance and microphonics when ceramic capacitors are used. While digital PLL can also have a reference spur due to finite steps of phase correction, this spur can be suppressed more easily because the digital loop filter makes it easy to implement very narrow loop bandwidths (<1 Hz). More important, because the loop characteristics are determined by digital coefficients, the loop dynamics are much more tightly controlled than in an analog PLL. This is a key advantage in phase-modulated systems.

In any PLL, reference noise within the PLL loop bandwidth is passed to the output, and reference noise outside the PLL loop bandwidth is attenuated. A key advantage to the dual-loop DDS-based digital PLL architecture is that the output phase noise is dependent on the DAC system clock, as opposed to the analog VCO. This allows designers to choose a system clock source that is tailored for specific jitter requirements. In an analog PLL, replacing one VCO with another will require matching the supply voltage, gain, frequency range, and other VCO parameters, which can be quite difficult. Another difficulty with the analog PLL is that the designer must trade off VCO tuning range for VCO phase noise, with VCO noise going up as the VCO frequency range is increased. The DDS digital PLL removes these constraints. By providing a clean DAC system clock, the designer will have the equivalent of a quiet wideband low-noise VCO. This allows the designer to select a low PLL loop bandwidth for jitter cleanup.

Because the phase detector gain, loop bandwidth, and phase margin are programmable in a digital PLL, the user can maintain the same loop transfer function for various conditions. For example, the user may need to synchronize to an 8 kHz BITS clock on one reference input, and a 19.44 MHz SONET/SDH reference clock on the other input to generate a 125 MHz reference clock for gigabit Ethernet. In a digital PLL, the loop filter can be optimized for constant loop bandwidth and phase margin for both cases. More important, the loop parameters can be adjusted as conditions warrant by programming registers instead of changing components.

A DDS-based digital PLL has another key advantage by having a high-speed DAC system clock available for reference monitoring. This clock can be used to oversample the reference inputs, and allows for rapid detection of reference clock drift or failure. Once a failure is detected, the device can automatically switch inputs or go into holdover mode. Hitless clock switching is easily implemented in the digital logic. Clock holdover occurs when both reference clocks fail, and the digital PLL will then act like a DDS frequency synthesizer and continue to output the same frequency for as long as necessary. The stability of the output clock in holdover mode is the same as the stability of the system clock. Accomplishing this with an analog PLL would require either an external oscillator that is a multiple of the reference input, or a voltage on the VCO that is stable to submicrovolt levels over temperature for long periods of time. While the former might be practical, the latter is not.