To further ease digital communication between a high-speed analog-to-digital converter (ADC) and FPGAs, Linear Technology has readied a new 16-bit 105 Msps part that establishes a new benchmark. The LTC2274's new high-speed two-wire serial interface greatly reduces the number of data input/output (I/O) lines required between a 16-bit ADC and the FPGA from 16 CMOS or 32 LVDS parallel data lines to a single, self-clocking, differential pair communicating at 2.1 Gbps. As a result, this frees up valuable FPGA pins.
Serial data communications offers simplified layout, and requires less board area for routing, while providing the flexibility to route across analog and digital boundaries. In noise-sensitive applications, the serial interface provides an effective isolation barrier between digital and analog circuitry and serves to eliminate coupling between digital outputs to reduce digital feedback.
The 0.35 µm CMOS-based LTC2274's output data is serialized according to the JEDEC serial interface specification for data converters (JESD204) using 8b10b encoding, and is compatible with many FPGA high-speed interfaces including Xilinx's Rocket IO, Altera's Stratix II GX I/O and Lattice's ECP2M I/O. At 2.1 Gbps, the LTC2274 offers the fastest high-speed serial interface of any ADC on the market today, claimed Alison Steer, product marketing manager for Linear's Mixed-Signal Division. Applications such as leading-edge communications equipment, multichannel systems, space-constrained designs, and instrumentation all benefit from the LTC2274's unique interface and feature set, noted Alison.
For high-sensitivity receiver applications, for instance, the LTC2274 provides an internal transparent dither circuit that improves the ADC's spurious-free dynamic range (SFDR) response well beyond 100 dBc for low-level input signals. To avoid any interference from the serial digital outputs, an optional data scrambler is available to randomize the spectrum of the serial link. Serial test patterns are also incorporated to facilitate testing of the serial interface. While the LTC2274 may be operated at a maximum sampling rate of 105 Msps, the internal PLL may be configured to lock at one of three different sample rate ranges. An on-chip clock duty cycle stabilizer circuit has been implemented to facilitate non-50% clock duty cycles. Separate shutdown pins for the analog and digital sections are provided to conserve power.
Consequently, it offers high signal-to-noise ratio (SNR) performance of 77.5 dB and SFDR of 100 dB at baseband. Ultralow jitter of 80 fs RMS enables undersampling of input frequencies up to 500 MHz with excellent noise performance. The LTC2274 consumes 1.3 W from a 3.3 V analog supply. And its serial output enables it to fit in a 6 mm × 6 mm QFN-40 package, less than half the size of similar 16-bit ADCs with parallel outputs. In addition to the 16-bit, 105 Msps LTC2274, pin-compatible 80 Msps and 65 Msps versions will be released this summer. Production quantities of the LTC2274 will be available in July in both commercial and industrial temperature grades. The device is priced at $68.00 each in 1,000-piece quantities.
Linear Technology Corp.