Xpedion Design Systems has unveiled the latest version of its GoldenGate simulator, version 3.5. This release of Xpedion's flagship product delivers another major advancement in convergence and speed for RFIC designers. GoldenGate 3.5 uses 50% less memory while doubling the speed over the previous version.

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These improvements allow design teams to tackle unprecedented amounts of characterization prior to tape-out, reducing design spins. Furthermore, design for yield analysis, such as Monte Carlo and sweeping process corners, become feasible for full transceiver radios. These capabilities enable designers to optimize their designs for high yield production.

"The impact of improving yield just a few percentage points is enormous to the bottom line of a successful radio project," said Pete Johnson, director of marketing at Xpedion. "GoldenGate 3.5 enables designers to perform Monte Carlo analysis as part of the typical design flow to accomplish these goals. Furthermore, tighter specifications and shorter design windows are driving designers to implement a Best Practices RFIC design methodology, of which GoldenGate is a significant contributor. "