Mobile devices with multimedia capability now incorporate richer, thinner, and lighter designs with increased needs for intensive integration and high bandwidth. This is possible with the evolution of submicron CMOS ICs toward lower lithography dimensions and increased use of system-in-package technology. These highly integrated and compact environments make ESD considerations even more important.

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The integration of on-chip ESD protection becomes more challenging, and the closer juxtaposition of the ICs to the external connectors makes the system protection (IEC 61000-4-2 standard compliance) even more difficult to achieve. veryVery efficient external ESD protection is required to sufficiently protect the very sensitive submicron CMOS ICs and comply with the IEC 61000-4-2 standard.

Submicron IC Evolution

Thinner lithography dimensions are required to improve circuit speed and address high-speed applications and richer content. As a matter of fact, the gate-oxide thickness enters the nanometer range. In 0.1-µm and smaller generations, the gate oxide of a transistor becomes increasingly thin (below 1.7 nm). This thinness results in a remarkable drop of the transistor’s oxide breakdown voltage.

As the oxides get thinner, the CDM performance gets lower. Similarly, as the metallization gets thinner, the resistance and the heating of the circuit increase. As a result, the circuit has lower CDM and HBM performances and is remarkably more sensitive to ESD.

ESD Council Targets

Circuit costs are a continuous concern for both circuit makers and users. As a result, the Industry Council on ESD target levels was initiated in 2006 to review on-chip ESD target levels. According to the ESD Council, the enhanced static control methods required by OEMs do not justify the current HBM and MMs.

In addition, everybody knows that the thinner the circuit lithography, the higher the technology cost. So according to the ESD Council, ESD overdesign in today’s high-integration technologies constrains chip area. Also, the cost of on-chip ESD protection becomes significant. Furthermore, the areas that ESD protection occupies have a significant impact on silicon performance, design cycle time, and time-to-market.

The gap in cost between the design necessary for safe handling and the design for 2-kV HBM sustainability has increased a lot, thanks to enhanced static control methods. Therefore, the ESD Council has proposed new ESD target levels downgrading the HBM and MM targets from 2 to 1 kV and from 200 to 30 V, respectively. However, the combination of thinner gate oxide and lower on-chip ESD protection levels will greatly decrease the robustness of the IC in ESD-risky environments like portable electronic applications.