With the foundation in place, the integration between the RF design tool and PCB needed an overhaul. For more than 10 years, this integration has been based on two-way translation of ASCII IFF-format files. Although, capable of holding a portion of the design data, this format is far from adequate to support seamless round-trip integration. Lack of library synchronization is one of the more critical issues. RF and board designers have struggled with this model for a long time and despite attempts to improve the interfaces only marginal results were seen.

Something different had to be developed and this led to a network-based inter-tool communication providing a dynamic two-way link between RF design and system-level PCB design (Figure 2). To support concurrent engineering processes, multiple board designers can operate simultaneously on the same design database and each link to one or multiple simulation sessions. Now an RF module can be designed in the RF design tool and, when appropriate, be pushed over and become an intelligently integrated part of the system-level schematic and PC board rather than the black box circuit of the past. At this stage, circuit updates can be made in either environment and the impact be simulated.

Each RF circuit is contained as a grouped object to help maintain traceability, version management and design reuse. As design intent is preserved, any number of iterations can be processed without the usual cost in cycle time. Also, as the RF module can be simulated within the context of the actual system-level PCB, its function can be validated at a more detailed level to help cut design cycles.

There are several well-known RF PCB design bottlenecks. First, as each RF module on a board may have been designed by a separate RF design team and the module may live its own life in terms of versioning, variants and reuse, it becomes vital to be able to manage the circuit as a group that can be managed as one entity and its origin and version be traced — but still be accessed as individual circuit elements at any time. To resolve this issue, the schematic and layout tools were expanded to support hierarchical circuit grouping. This way, even though an RF circuit is laid out on a PCB, it is still kept together as an RF circuit and can be linked to the proper RF team for analysis.

The next hurdle is ground plane clearance. In the classic design process, the RF metal was imported as a black box piece of metal and ground clearance was handcrafted as plane voids on every layer needed. When the RF circuit was updated — which was a frequent operation — the cutouts had to be manually edited to reflect the new circuit. This edit process alone can take weeks for some designs.

With a new design flow that promotes iterative updates between RF design and PCB design; manual updating is too slow. Instead, an intelligent parametric RF shape clearance is introduced to let the RF circuit clear ground the way the RF engineer defines it, and to have it parametrically updated as the RF circuit evolves during design, as shown in Figure 3. This parametric plane clearance cannot only be defined for the same layer on which the RF shape is placed, but also for layers above and below the shape, including the solder mask. If the RF circuit is updated with changed dimensions or if it's being moved to a new layer, these cutouts automatically update, saving a tremendous amount of cycle time.

Interconnection between RF elements on the PCB typically uses meander lines instead of normal PCB traces to connect RF circuits. These meander lines can have tapered width changes, optimal impedance miter, or curved bends.

In the past these were made as metal plane shapes and were difficult to edit. Furthermore, as they were metal polygons, the only way to simulate was to use a time-consuming EM solution. Mentor has solved this dilemma by designing a meander line design object for its PCB tools. This way, the PCB designer can connect RF signals effectively and when simulation is needed, the meander lines can be sent to EM analysis — as in the past — or automatically be decomposed into fast circuit models.

A striking feature of most RF system designs is the very large number of via holes stitched along RF shapes, around plane contours or peppered over plane surfaces.

This so-called via stitching is used to reduce radiation losses when stitched along RF shapes or when peppered across planes, to prevent parallel plane excitation.

Adding these vias manually costs countless hours or days and need manual rework each time the circuit is updated in design iteration. Many board designers developed smart scripts and programs to add the vias but the issue with rework is still unsolved.

Now, designers can automatically generate via patterns and contour stitching parametrically in elaborate patterns, multirow stitching along shapes, and include them in the EM simulation (Figure 3).

The new RF design paradigm has put RF design companies in a tricky situation with unacceptable cycle time and excessive design cycles. We are now working with RF tool vendors at a different level than what has been the norm in order to provide a design flow that is tailored to meet the challenges seen in the industry today and in the future.

The prime goal — to cut design cycles — is reached by ensuring a synchronized library and by facilitating a fast and easy integrated simulation flow. As designers can simulate frequently as the design evolves, the system can be validated up front. RF-aware DRC promoting correct by design also contributes.

Cycle time was traditionally wasted in cumbersome file translation between tools and in the fact that the PCB tools did not understand RF or even support some of the primary RF design requirements.

ASCII file transfer is a relic of the past. The demand for integrated design teams across technology and global boundaries dictates direct tool integration where the tool sets share an understanding of RF.

Per Viklund is director of RF and IC Packaging at Mentor Graphics' Systems Design Division.

John Isaac is marketing development manager for Mentor Graphics' Systems Design Division.

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