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Optimizing Power

The best solution uses a voltage controlled dc-dc converter that dynamically adjusts the RFPA supply voltage to continuously achieve the highest possible power efficiency for each RF power level. This technique is called DVS, or dynamic voltage scaling (Fig. 2).

Figure 3 shows the improvement of an RFPA’s PAE using the DVS power-management scheme (blue curve) compared to an RFPA directly supplied from the battery (black). It also shows a battery current savings of about 100 mA for a power range of 16 to 24 dBm and about 10 mA from 0 to 16 dBm. In other words, a 3G data-centric handset using the DVS solution can save up to 20% of the battery power and proportionally extend the data connection time.

While using the DVS technique, it’s also important to clamp the RFPA supply level to 3.4 V when the battery is charged up to 4.2 V. (Note: 3.4 V is the optimum supply level for most RFPAs available on the market.) This results in a 20% additional reduction of heating that happens at high battery levels. It also enables designers to reduce the size of the heatsink and/or the spacing between the components integrated on the same printed-circuit board (PCB).

A single-mode RFPA using DVS (blue curve) offers better PAE than a two-mode W-CDMA RFPA (black curve).

Furthermore, with a DVS power-management solution, the RF engineers could replace the sophisticated multi-power-mode RFPAs with single-power-mode PAs and improve power efficiency, reduce power heating, and lower the bill of materials (BOM) cost.

The dc-dc suppliers, then, need to provide compact solutions that fit inside RF front-end modules without polluting the baseband or the RF spectrum. The real challenge is to replace the bulky inductors (~10 mm2) by sub-µH inductors (3.2 mm2) by pushing the switching frequency and the switching noise beyond the baseband frequency (>5 MHz).

Sami Ajram manages power-management products dedicated to RF transceivers in mobile communication devices at Fairchild Semiconductor. He graduated in 1994 from the University of Sciences and Technologies of Lille (USTL) in France as an MSc in electronics with a major in RF system design. He pursued his research program working on ultra-high-frequency switching converters where he published the first 100-MHz, 3-W boost converter using an air core inductor. He defended his PhD in 1998 and continued at the USTL as a research and teaching assistant. He led the development of a 20GSa/s real-time sampler based on 0.15-µm P-HEMT MMIC technology before joining in 2000 the ASIC group at ATMEL in France. He led several IP developments in 0.5-µm down to 0.13-µm CMOS processes, including clock synthesis and low-noise analog front-end IP.